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june 2006 rev 1 1/229 1 st10f276 16-bit mcu with mac unit, 832 kbyte flas h memory and 68 kbyte ram features highly performant 16-bit cpu with dsp functions ? 31.25ns instruction cycle time at 64mhz max cpu clock ? multiply/accumulate unit (mac) 16 x 16-bit multiplication, 40 -bit accumulator ? enhanced boolean bit manipulations ? single-cycle context switching support on-chip memories ? 512 kbyte flash memory (32-bit fetch) ? 320 kbyte extension flash memory (16-bit fetch) ? single voltage flash memories with erase/program controller and 100k erasing/programming cycles. ? up to 16 mbyte linear address space for code and data (5 mbytes with can or i 2 c) ? 2 kbyte internal ram (iram) ? 66 kbyte extension ram (xram) external bus ? programmable external bus configuration & characteristics for different address ranges ? five programmable chip-select signals ? hold-acknowledge bus arbitration support interrupt ? 8-channel peripheral event controller for single cycle interrupt driven data transfer ? 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns timers ? two multi-functional general purpose timer units with 5 timers two 16-channel capture / compare units 4-channel pwm unit + 4-channel xpwm a/d converter ? 24-channel 10-bit ?3 s minimum conversion time serial channels ? two synch. / asynch. serial channels ? two high-speed synchronous channels ?one i 2 c standard interface 2 can 2.0b interfaces operating on 1 or 2 can busses (64 or 2x32 message, c-can version) fail-safe protection ? programmable watchdog timer ? oscillator watchdog on-chip bootstrap loader clock generation ? on-chip pll with 4 to 12 mhz oscillator ? direct or prescaled clock input real time clock and 32 khz on-chip oscillator up to 111 general purpose i/o lines ? individually programmable as input, output or special function ? programmable threshold (hysteresis) idle, power down and stand-by modes single voltage supply: 5v 10% (embedded regulator for 1.8 v core supply) pqfp144 (28 x 28 x 3.4mm) (plastic quad flat package) lqfp144 (20 x 20 x 1.4mm) (low profile quad flat package) order codes part number package max cpu frequency iflash xflash ram temperature range (c) st10f276z5q3 pqfp144 64 mhz 512kb 320kb 68kb -40/+125 st10f276z5t3 lqfp144 40 mhz 512kb 320kb 68kb -40/+125 www.st.com
contents st10f276 2/229 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 internal flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.1 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.2 modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2.3 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 power supply drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4.1 flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4.2 flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.3 flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4.4 flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.5 flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.6 flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.7 flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.8 flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.9 flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.10 flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.11 flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.12 xflash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.1 protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.2 flash non volatile write protection x register low . . . . . . . . . . . . . . . . . . 37 4.5.3 flash non volatile write protection x register high . . . . . . . . . . . . . . . . . 38 4.5.4 flash non volatile write protection i register low . . . . . . . . . . . . . . . . . . 38 4.5.5 flash non volatile write protection i register high . . . . . . . . . . . . . . . . . . 38 4.5.6 flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 39
st10f276 contents 3/229 4.5.7 flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 39 4.5.8 flash non volatile access protection register 1 high . . . . . . . . . . . . . . . 40 4.5.9 access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.10 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5.11 temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5 bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.1 selection among user-code, standard or alternate bootstrap . . . . . . . . . 46 5.2 standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2.1 entering the standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2.2 st10 configuration in bsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2.3 booting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2.4 hardware to activate bsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2.5 memory configuration in bootstrap loader mode . . . . . . . . . . . . . . . . . . 51 5.2.6 loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.7 exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2.8 hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 standard bootstrap with uart (rs232 or k-line) . . . . . . . . . . . . . . . . . . 53 5.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.2 entering bootstrap via uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.3 st10 configuration in uart bsl (rs232 or k-line) . . . . . . . . . . . . . . 55 5.3.4 loading the start-up code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.5 choosing the baud rate for the bsl via uart . . . . . . . . . . . . . . . . . . . 56 5.4 standard bootstrap with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4.2 entering the can bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.4.3 st10 configuration in can bsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.4.4 loading the start-up code via can . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.4.5 choosing the baud rate for the bsl via can . . . . . . . . . . . . . . . . . . . . 60 5.4.6 computing the baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4.7 bootstrap via can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.5 comparing the old and the new bootstrap loader . . . . . . . . . . . . . . . . . . 64 5.5.1 software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.5.2 hardware aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
contents st10f276 4/229 5.6 alternate boot mode (abm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.1 activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6.4 st10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 66 5.6.5 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.6.6 exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.6.7 alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.6.8 user/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 67 5.6.9 alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.6.10 emucon register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.6.11 internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.6.12 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.7 selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6 central processing unit (cpu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.1 multiplier-accumulator unit (mac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 mac coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.1 x-peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2 exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9 capture / compare (capcom) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10 general purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.1 gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.2 gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11 pwm modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.2 i/o?s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
st10f276 contents 5/229 12.2.1 open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2.2 input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14 serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.1 asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 94 14.2 ascx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.3 ascx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.4 high speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 96 15 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 16 can modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 16.1 configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 16.2 can bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 17 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 19.1 input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 19.2 asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 19.3 synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 19.4 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 19.5 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 19.6 bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 19.7 reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 19.8 reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 19.9 reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 20 power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 20.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 20.2 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
contents st10f276 6/229 20.2.1 protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 20.2.2 interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 20.3 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 20.3.1 entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 20.3.2 exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 20.3.3 real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 20.3.4 power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 21 programmable output clock divi der . . . . . . . . . . . . . . . . . . . . . . . . . . 135 22 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 22.1 register description format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 22.2 general purpose registers (gprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 22.3 special function registers ordered by name . . . . . . . . . . . . . . . . . . . . . 139 22.4 special function registers ordered by address . . . . . . . . . . . . . . . . . . . . 146 22.5 x-registers sorted by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 22.6 x-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 22.7 flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 22.8 flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 22.9 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 22.10 system configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 22.10.1 xpercon and xperemu registers . . . . . . . . . . . . . . . . . . . . . . . . . 174 22.11 emulation dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 23 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 23.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 23.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 23.3 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 23.4 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 23.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 23.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 23.7 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 23.7.1 conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 23.7.2 a/d conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 23.7.3 total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
st10f276 contents 7/229 23.7.4 analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 23.7.5 analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 23.7.6 example of external network sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 23.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 23.8.1 test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 23.8.2 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 23.8.3 clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 23.8.4 prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 23.8.5 direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 23.8.6 oscillator watchdog (owd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 23.8.7 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 23.8.8 voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 23.8.9 pll jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 23.8.10 jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 23.8.11 noise in the pll loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 23.8.12 pll lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23.8.13 main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23.8.14 32 khz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 23.8.15 external clock drive xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 23.8.16 memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 23.8.17 external memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23.8.18 multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 23.8.19 demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 23.8.20 clkout and ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 23.8.21 external bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 23.8.22 high-speed synchronous serial interface (ssc) timing modes . . . . . . 222 24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 25 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
list of tables st10f276 8/229 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. flash modules absolute mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 3. flash modules sectorization (read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4. flash modules sectorization (write operations or with roms1=?1?) . . . . . . . . . . . . . . . . . . . 26 table 5. control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. banks (bxs) and sectors (bxfy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. xflash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. flash non volatile write protection x register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. flash non volatile write protection x register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 21. flash non volatile write protection i register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. flash non volatile write protection i register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24. flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 25. flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 26. summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 27. flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 28. st10f276 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. st10 configuration in bsl mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 30. st10 configuration in uart bsl mode (rs232 or k-line). . . . . . . . . . . . . . . . . . . . . . . . . 55 table 31. st10 configuration in can bsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 32. brp and pt0 values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 33. software topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 34. hardware topics summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 35. st10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. abm bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. selective boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 38. standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 39. mac instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 40. interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 41. x-interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 42. trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 43. compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 44. capcom timer input frequencies, resolutions and periods at 40 mhz . . . . . . . . . . . . . . . 83 table 45. capcom timer input frequencies, resolutions and periods at 64 mhz . . . . . . . . . . . . . . . 83 table 46. gpt1 timer input frequencies, resolutions and periods at 40 mhz. . . . . . . . . . . . . . . . . . . 84 table 47. gpt1 timer input frequencies, resolutions and periods at 64 mhz. . . . . . . . . . . . . . . . . . . 85 table 48. gpt2 timer input frequencies, resolutions and periods at 40 mhz. . . . . . . . . . . . . . . . . . . 86
st10f276 list of tables 9/229 table 49. gpt2 timer input frequencies, resolutions and periods at 64 mhz. . . . . . . . . . . . . . . . . . . 86 table 50. pwm unit frequencies and resolutions at 40 mhz cpu clock . . . . . . . . . . . . . . . . . . . . . . 88 table 51. pwm unit frequencies and resolutions at 64 mhz cpu clock . . . . . . . . . . . . . . . . . . . . . . 88 table 52. asc asynchronous baud rates by reload value and deviation errors (fcpu = 40 mhz) . . 94 table 53. asc asynchronous baud rates by reload va lue and deviation errors (fcpu = 64 mhz) . . 95 table 54. asc synchronous baud rates by reload value and deviation errors (fcpu = 40 mhz) . . . 95 table 55. asc synchronous baud rates by reload value and deviation errors (fcpu = 64 mhz) . . . 96 table 56. synchronous baud rate and reload values (fcpu = 40 mhz). . . . . . . . . . . . . . . . . . . . . . . 97 table 57. synchronous baud rate and reload values (fcpu = 64 mhz). . . . . . . . . . . . . . . . . . . . . . . 97 table 58. wdtrel reload value (fcpu = 40 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 59. wdtrel reload value (fcpu = 64 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 60. reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 61. reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 62. port0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 128 table 63. power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 64. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 65. general purpose registers (gprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 table 66. general purpose registers (gprs) bytewise addressing. . . . . . . . . . . . . . . . . . . . . . . . . 137 table 67. special function registers ordered by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 68. special function registers ordered by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 69. x-registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 70. x-registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 71. flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 72. flash registers ordered by address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 73. manuf description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 74. idchip description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 75. idmem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 76. idprog description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 77. syscon description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 78. buscon4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 79. rpoh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 80. exixes bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 81. exisel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 82. exixss and port 2 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 table 83. sfr area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 84. esfr description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 85. segment 8 address range mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 86. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 87. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 88. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 89. package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 90. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 91. flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 92. data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 94. a/d converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 95. on-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 96. internal pll divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 97. pll lock/unlock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 98. main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 99. negative resistance (absolute min. value @125o c / vdd = 4.5v). . . . . . . . . . . . . . . . . . 202 table 100. 32 khz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 101. minimum values of negative resistance (module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
list of tables st10f276 10/229 table 102. external clock drive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 103. memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 104. multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 105. demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 106. clkout and ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 107. external bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 108. master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 109. slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 110. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
st10f276 list of figures 11/229 list of figures figure 1. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2. pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. st10f276 new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6. booting steps for st10f276 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 7. hardware provisions to activate the bsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 8. memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 9. uart bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figure 10. baud rate deviation between host and st10f276 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 11. can bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 12. bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 13. reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 14. cpu block diagram (mac unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 15. mac unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 16. x-interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 17. block diagram of gpt1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 18. block diagram of gpt2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 19. block diagram of pwm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 20. connection to single can bus via separate can transceivers . . . . . . . . . . . . . . . . . . . . 100 figure 21. connection to single can bus via common can transceivers. . . . . . . . . . . . . . . . . . . . . 100 figure 22. connection to two different can buses (e.g. for gateway application). . . . . . . . . . . . . . . 101 figure 23. connection to one can bus with internal parallel mode enabled . . . . . . . . . . . . . . . . . . 101 figure 24. asynchronous power-on reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 25. asynchronous power-on reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 26. asynchronous hardware reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 27. asynchronous hardware reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 28. synchronous short / long ha rdware reset (ea = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 29. synchronous short / long ha rdware reset (ea = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 30. synchronous long hardware reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 31. synchronous long hardware reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 32. sw / wdt unidirectional reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 33. sw / wdt unidirectional reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 34. sw / wdt bidirectional reset (ea=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 35. sw / wdt bidirectional reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 36. sw / wdt bidirectional r eset (ea=0) followed by a hw reset . . . . . . . . . . . . . . . . . 122 figure 37. minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 38. system reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 39. internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 40. example of software or watchdog bidirectional reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . 125 figure 41. example of software or watchdog bidirectional reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . 126 figure 42. port0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 43. external rc circuitry on rpd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 44. port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 45. supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . 182 figure 46. a/d conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 47. a/d converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 48. charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 190
list of figures st10f276 12/229 figure 49. anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 50. input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 51. float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 52. generation mechanisms for the cpu clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 53. st10f276 pll jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 54. crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 55. 32 khz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 56. external clock drive xtal1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 57. multiplexed bus with/without r/w delay and normal ale. . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 58. multiplexed bus with/without r/w delay and extended ale . . . . . . . . . . . . . . . . . . . . . . . 209 figure 59. multiplexed bus, with/without r/w delay, normal ale, r/w cs. . . . . . . . . . . . . . . . . . . . 210 figure 60. multiplexed bus, with/without r/ w delay, extended ale, r/w cs . . . . . . . . . . . . . . . . . 211 figure 61. demultiplexed bus, with/without read/write delay and normal ale . . . . . . . . . . . . . . . . . 214 figure 62. demultiplexed bus with/without r/w delay and extended ale . . . . . . . . . . . . . . . . . . . . 215 figure 63. demultiplexed bus with ale and r/w cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 64. demultiplexed bus, no r/w delay, extended ale, r/w cs . . . . . . . . . . . . . . . . . . . . . . . 217 figure 65. clkout and ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 66. external bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 0 figure 67. external bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1 figure 68. ssc master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 69. ssc slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 70. 144-pin plastic quad flat package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 71. 144-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
st10f276 introduction 13/229 1 introduction the st10f276 is a derivative of the stmicr oelectronics st10 family of 16-bit single-chip cmos microcontrollers. it comb ines high cpu performance ( up to 32 million instructions per second) with high peripheral functionality a nd enhanced i/o-c apabilities. it also provides on-chip high-speed single voltage flash memory, on-chip high-speed ram, and clock generation via pll. st10f276 is processed in 0.18 m cmos technology. the mcu core and the logic is supplied with a 5v to 1.8v on-chip voltage regulator. the part is supplied with a single 5v supply and i/os work at 5v. the device is upward compatible with the st10f269 device, with the following set of differences: flash control interface is now based on stmicroelectronics third generation of stand- alone flash memories (m29f400 series), wi th an embedded program/erase controller. this completely frees up the cpu during programming or erasing the flash. only one supply pin (ex dc1 in st10f269, renamed into v 18 ) on the qfp144 package is used for decoupling the internally generated 1.8v core logic supply. do not connect this pin to 5.0v external supply. instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10nf, maximum value 100nf). the ac and dc parameters are modified due to a difference in the maximum cpu frequency. a new v dd pin replaces dc2 of st10f269. ea pin assumes a new alternate functionality: it is also used to provide a dedicated power supply (see v stby ) to maintain biased a portion of the xram (16kbytes) when the main power supply of the device (v dd and consequently the internally generated v 18 ) is turned off for low power mo de, allowing data retention. v stby voltage shall be in the range 4.5-5.5 volt, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8v for the ram, th e low-voltage section of the 32khz oscillator and the real time clock module when not disabled. it is allowed to exceed the upper limit up to 6v for a very short period of time during the global life of the device, and exceed the lower limit down to 4v when rtc and 32khz on-chi p oscillator are not used. a second ssc mapped on the xbus is added (ssc of st10f269 becomes here ssc0, while the new one is referred as xssc or simply ssc1). note that some restrictions and functional differences due to the xbus peculiarities are present between the classic ssc, and the new xssc. a second asc mapped on the xbus is added (asc0 of st10f269 remains asc0, while the new one is referred as xasc or simply as asc1). no te that some restrictions and functional differences due to the xbus peculiarities are present between the classic asc, and the new xasc. a second pwm mapped on the xbus is added (pwm of st10f269 becomes here pwm0, while the new one is referred as xpwm or simply as pwm1). note that some
introduction st10f276 14/229 restrictions and functional differences due to the xbus peculiarities are present between the classic pwm, and the new xpwm. an i 2 c interface on the xbus is added (see x-i 2 c or simply i 2 c interface). clkout function can output either the cpu clock (like in st10f269) or a software programmable prescaled value of the cpu clock. embedded memory size has been significantly increased (both flash and ram). pll multiplication factors have been adapted to new frequency range. a/d converter is not fully compatible versus st10f269 (timing and programming model). formula for the convertion time is still valid, while the sampling phase programming model is different. besides, additional 8 channels are available on p1l pins as alternate function: the accuracy reachable with these extra channels is reduced with respect to the standard port5 channels. external memory bus potential limitations on maximum speed and maximum capacitance load could be in troduced (under evaluation ): st10f276 will probably not be able to address an external memory at 64mhz with 0 wait states (under evaluation). xpercon register bit mapping modified acco rding to new perip herals implementation (not fully compatible with st10f269). bondout chip for emulation (st10r201) cannot achieve more than 50mhz at room temperature (so no real time emulation possible at maximum speed). input section characteristics are different. the threshold programma bility is extended to all port pins (additional xpicon register); it is possible to select standard ttl (with up to 500mv of hysteresis) and standard cmos (with up to 800mv of hysteresis). output transition is not programmable. can module is enhanced: st10f276 impl ements two c-can modules, so the programming model is slightly different. beside s, the possibility to map in parallel the two can modules is added (on p4.5/p4.6). on-chip main oscillator input frequency range has been resh aped, reducing it from 1- 25mhz down to 4-12mhz. this is a high pe rformance oscillator amplifier, providing a very high negative resistance and wide oscillation amplitude: when this on-chip amplifier is used as reference for re al time clock module, the power-down consumption is dominated by the consumption of the oscillator amplif ier itself. a metal option is added to offer a low power oscillato r amplifier working in the range of 4-8mhz: this will allow a power consumption reductio n when real time clock is running in power down mode using as reference the on-chip main oscillator clock. a second on-chip oscillator amplifier circui t (32khz) is implem ented for low power modes: it can be used to provide the reference to the real time clock counter (either in power down or stand-by mode). pin xtal3 and xtal4 replace a couple of v dd /v ss pins of st10f269. possibility to re-program inte rnal xbus chip select windo w characteristics (xram2 and xflash address window) is added.
st10f276 introduction 15/229 figure 1. logic symbol xtal1 rstin xtal2 rstout nmi ea / v stby ready ale rd wr / wrl port 5 16-bit port 6 8-bit port 4 8-bit port 3 15-bit port 2 16-bit port 1 16-bit port 0 16-bit v dd v ss port 7 8-bit port 8 8-bit v aref v agnd st10f276 v 18 xtal3 xtal4 rpd
pin data st10f276 16/229 2 pin data figure 2. pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p6.0 / cs0 p6.1 / cs1 p6.2 / cs2 p6.3 / cs3 p6.4 / cs4 p6.5 / hold / sclk1 p6.6 / hlda / mtsr1 p6.7 / breq / mrst1 p8.0 / xpout0 / cc16io p8.1 / xpout1 / cc17io p8.2 / xpout2 / cc18io p8.3 / xpout3 / cc19io p8.4 / cc20io p8.5 / cc21io p8.6 / rxd1 / cc22io p8.7 / txd1 / cc23io vdd vss p7.0 / pout0 p7.1 / pout1 p7.2 / pout2 p7.3 / pout3 p7.4 / cc28io p7.5 / cc29io p7.6 / cc30io p7.7 / cc31io p5.0 / an0 p5.1 / an1 p5.2 / an2 p5.3 / an3 p5.4 / an4 p5.5 / an5 p5.6 / an6 p5.7 / an7 p5.8 / an8 p5.9 / an9 p0h.0 / ad8 p0l.7 / ad7 p0l.6 / ad6 p0l.5 / ad5 p0l.4 / ad4 p0l.3 / ad3 p0l.2 / ad2 p0l.1 / ad1 p0l.0 / ad0 ea / vstby ale ready wr /wrl rd vss vdd p4.7 / a23 / can2_txd / sda p4.6 / a22 / can1_txd / can2_txd p4.5 / a21 / can1_rxd / can2_rxd p4.4 / a20 / can2_rxd / scl p4.3 / a19 p4.2 / a18 p4.1 / a17 p4.0 / a16 rpd vss vdd p3.15 / clkout p3.13 / sclk0 p3.12 / bhe / wrh p3.11 / rxd0 p3.10 / txd0 p3.9 / mtsr0 p3.8 / mrst0 p3.7 / t2in p3.6 / t3in varef vagnd p5.10 / an10 / t6eud p5.11 / an11 / t5eud p5.12 / an12 / t6in p5.13 / an13 / t5in p5.14 / an14 / t4eud p5.15 / an15 / t2eud vss vdd p2.0 / cc0io p2.1 / cc1io p2.2 / cc2io p2.3 / cc3io p2.4 / cc4io p2.5 / cc5io p2.6 / cc6io p2.7 / cc7io vss v18 p2.8 / cc8io / ex0in p2.9 / cc9io / ex1in p2.10 / cc10io / ex2in p2.11 / cc11io / ex3in p2.12 / cc12io / ex4in p2.13 / cc13io / ex5in p2.14 / cc14io / ex6in p2.15 / cc15io / ex7in / t7in p3.0 / t0in p3.1 / t6out p3.2 / capin p3.3 / t3out p3.4 / t3eud p3.5 / t4in vss vdd xtal4 xtal3 nmi rstout rstin vss xtal1 xtal2 vdd p1h.7 / a15 / cc27i p1h.6 / a14 / cc26i p1h.5 / a13 / cc25i p1h.4 / a12 / cc24i p1h.3 / a11 p1h.2 / a10 p1h.1 / a9 p1h.0 / a8 vss vdd p1l.7 / a7 / an23 (*) p1l.6 / a6 / an22 (*) p1l.5 / a5 / an21 (*) p1l.4 / a4 / an20 (*) p1l.3 / a3 / an19 (*) p1l.2 / a2 / an18 (*) p1l.1 / a1 / an17 (*) p1l.0 / a0 / an16 (*) p0h.7 / ad15 p0h.6 / ad14 p0h.5 / ad13 p0h.4 / ad12 p0h.3 / ad11 p0h.2 / ad10 p0h.1 / ad9 vss vdd st10f276
st10f276 pin data 17/229 table 1. pin description symbol pin type function p6.0 - p6.7 1 - 8 i/o 8-bit bidirectional i/o port, bit-wise prog rammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 6 outputs ca n be configured as push-pull or open drain drivers. the input threshold of po rt 6 is selectable (ttl or cmos). the following port 6 pins have alternate functions: 1op6.0cs0 chip select 0 output ... ... ... ... ... 5op6.4cs4 chip select 4 output 6 ip6.5hold external master hold request input i/o sclk1 ssc1: master clock output / slave clock input 7 o p6.6 hlda hold acknowledge output i/o mtsr1 ssc1: master-transmi tter / slave-receiver o/i 8 op6.7 breq bus request output i/o mrst1 ssc1: master-receiver / slave-transmitter i/o p8.0 - p8.7 9-16 i/o 8-bit bidirectional i/o port, bit-wise prog rammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 8 outputs ca n be configured as push-pull or open drain drivers. the input threshold of port 8 is selectable (ttl or cmos). the following port 8 pins have alternate functions: 9 i/o p8.0 cc16io capcom2: cc16 c apture input / compare output o xpwm0 pwm1: channel 0 output ... ... ... ... ... 12 i/o p8.3 cc19io capcom2: cc19 c apture input / compare output o xpwm0 pwm1: channel 3 output 13 i/o p8.4 cc20io capcom2: cc20 c apture input / compare output 14 i/o p8.5 cc21io capcom2: cc21 c apture input / compare output 15 i/o p8.6 cc22io capcom2: cc22 c apture input / compare output i/o rxd1 asc1: data input (asynch ronous) or i/o (synchronous) 16 i/o p8.7 cc23io capcom2: cc23 c apture input / compare output o txd1 asc1: clock / data output (asynchronous/synchronous)
pin data st10f276 18/229 p7.0 - p7.7 19-26 i/o 8-bit bidirectional i/o port, bit-wise prog rammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 7 outputs ca n be configured as push-pull or open drain drivers. the input threshold of port 7 is selectable (ttl or cmos). the following port 7 pins have alternate functions: 19 o p7.0 pout0 pwm0: channel 0 output ... ... ... ... ... 22 o p7.3 pout3 pwm0: channel 3 output 23 i/o p7.4 cc28io capcom2: cc28 c apture input / compare output ... ... ... ... ... 26 i/o p7.7 cc31io capcom2: cc31 c apture input / compare output p5.0 - p5.9 p5.10 - p5.15 27-36 39-44 i i 16-bit input-only port with schmitt-trigge r characteristics. the pins of port 5 can be the analog input channels (up to 16) for the a/d converter, where p5.x equals anx (analog input channel x), or they ar e timer inputs. the input threshold of port 5 is selectable (ttl or cmos). the following port 5 pins have alternate functions: 39 i p5.10 t6eud gpt2: timer t6 external up/down control input 40 i p5.11 t5eud gpt2: timer t5 external up/down control input 41 i p5.12 t6in gpt2: timer t6 count input 42 i p5.13 t5in gpt2: timer t5 count input 43 i p5.14 t4eud gpt1: timer t4 external up/down control input 44 i p5.15 t2eud gpt1: timer t2 external up/down control input p2.0 - p2.7 p2.8 - p2.15 47-54 57-64 i/o 16-bit bidirectional i/o port, bit-wise pr ogrammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 2 ou tputs can be configured as push-pull or open drain drivers. the input threshold of port 2 is selectable (ttl or cmos). the following port 2 pins have alternate functions: 47 i/o p2.0 cc0io capcom: cc0 capture input/compare output ... ... ... ... ... 54 i/o p2.7 cc7io capcom: cc7 capture input/compare output 57 i/o p2.8 cc8io capcom: cc8 capture input/compare output i ex0in fast external interrupt 0 input ... ... ... ... ... 64 i/o p2.15 cc15io capcom: cc15 capture input/compare output i ex7in fast external interrupt 7 input i t7in capcom2: timer t7 count input table 1. pin description (continued) symbol pin type function
st10f276 pin data 19/229 p3.0 - p3.5 p3.6 - p3.13, p3.15 65-70, 73-80, 81 i/o i/o i/o 15-bit (p3.14 is missing) bidirectional i/o port, bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 3 outputs can be configured as push-pull or open drain driv ers. the input threshold of port 3 is selectable (ttl or cmos). the following port 3 pins have alternate functions: 65 i p3.0 t0in capcom1: timer t0 count input 66 o p3.1 t6out gpt2: timer t6 toggle latch output 67 i p3.2 capin gpt2: register caprel capture input 68 o p3.3 t3out gpt1: timer t3 toggle latch output 69 i p3.4 t3eud gpt1: timer t3 external up/down control input 70 i p3.5 t4in gpt1; timer t4 input for count/gate/reload/capture 73 i p3.6 t3in gpt1: timer t3 count/gate input 74 i p3.7 t2in gpt1: timer t2 input for count/gate/reload / capture 75 i/o p3.8 mrst0 ssc0: master-receiver/slave-transmitter i/o 76 i/o p3.9 mtsr0 ssc0: master-transmitter/slave-receiver o/i 77 o p3.10 txd0 asc0: clock / data output (asynchronous/synchronous) 78 i/o p3.11 rxd0 asc0: data input (a synchronous) or i/o (synchronous) 79 o p3.12 bhe external memory high byte enable signal wrh external memory high byte write strobe 80 i/o p3.13 sclk0 ssc0: master clock output / slave clock input 81 o p3.15 clkout system clock output (programmable divider on cpu clock) table 1. pin description (continued) symbol pin type function
pin data st10f276 20/229 p4.0 ?p4.7 85-92 i/o port 4 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. the input threshold is selectable (ttl or cmos). port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open drain drivers. in case of an external bus configuration, port 4 can be used to output the segment address lines: 85 o p4.0 a16 segment address line 86 o p4.1 a17 segment address line 87 o p4.2 a18 segment address line 88 o p4.3 a19 segment address line 89 o p4.4 a20 segment address line i can2_rxd can2: receive data input i/o scl i 2 c interface: serial clock 90 o p4.5 a21 segment address line i can1_rxd can1: receive data input i can2_rxd can2: receive data input 91 o p4.6 a22 segment address line o can1_txd can1: transmit data output o can2_txd can2: transmit data output 92 o p4.7 a23 most significant segment address line o can2_txd can2: transmit data output i/o sda i 2 c interface: serial data rd 95 o external memory read strobe. rd is activated for every external instruction or data read access. wr /wrl 96 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in the syscon register for mode selection. ready/ ready 97 i ready input. the active level is programmable. when the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitst ate cycles until the pin returns to the selected active level. ale 98 o address latch enable output. in case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. table 1. pin description (continued) symbol pin type function
st10f276 pin data 21/229 ea / v stby 99 i external access enable pin. a low level applied to this pin during and after reset forces the st10f276 to start the program from the external memory space. a high level forces st10f276 to start in the internal memory space. this pin is also used (when stand-by mode is entered, that is st10f276 under reset and main v dd turned off) to bias the 32 khz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8v supply for the rtc module (when not disabled) and to retain data inside the stand-by portion of the xram (16kbyte). it can range from 4.5 to 5.5v (6v for a reduced amount of time during the device life, 4.0v when rtc and 32 khz on-chip oscillator amplifier are turned off). in running mode, this pin can be tied low during reset without affecting 32 khz oscillator, rtc and xram activities, since the presence of a stable v dd guarantees the proper biasing of all those modules. p0l.0 -p0l.7, p0h.0 p0h.1 - p0h.7 100-107, 108, 111-117 i/o two 8-bit bidirectional i/o ports p0l and p0h, bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. the input threshold of port 0 is selectable (ttl or cmos). in case of an external bus configuratio n, port0 serves as the address (a) and as the address / data (ad) bus in mult iplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes multiplexed bus modes p1l.0 - p1l.7 p1h.0 - p1h.7 118-125 128-135 i/o two 8-bit bidirectional i/o ports p1l and p1h, bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port1 is used as the 16- bit address bus (a) in demultiplexed bus modes: if at least busconx is configured such the demultiplexed mode is selected, the pis of port1 are not available for general purpose i/o function. the input threshold of port 1 is selectable (ttl or cmos). the pins of p1l also serve as the additional (up to 8) analog input channels for the a/d converter, where p1l.x equals any (analog input channel y, where y = x + 16). this additional function have higher priority on demultiplexed bus function. the following port1 pins have alternate functions: 132 i p1h.4 cc24io capcom2: cc24 capture input 133 i p1h.5 cc25io capcom2: cc25 capture input 134 i p1h.6 cc26io capcom2: cc26 capture input 135 i p1h.7 cc27io capcom2: cc27 capture input table 1. pin description (continued) symbol pin type function data path width 8-bit 16-bi p0l.0 ? p0l.7: d0 ? d7 d0 - d7 p0h.0 ? p0h.7: i/o d8 - d15 data path width 8-bit 16-bi p0l.0 ? p0l.7: ad0 ? ad7 ad0 - ad7 p0h.0 ? p0h.7: a 8 ? a15 a d8 - ad15
pin data st10f276 22/229 xtal1 138 i xtal1 main oscillator amplifier circuit and/or external clock input. xtal2 137 o xtal2 main oscillator amplifier circuit output. to clock the device from an external source, drive xtal1 while leaving xtal2 unconnected. minimum and maximum high / low and rise / fall times specified in the ac characteristics must be observed. xtal3 143 i xtal3 32 khz oscillator amplifier circuit input xtal4 144 o xtal4 32 khz oscillator amplifier circuit output when 32 khz oscillator amplifier is not used, to avoid spurious consumption, xtal3 shall be tied to ground while xtal4 shall be left open. besides, bit off32 in rtccon register shall be set. 32 khz oscillator can only be driven by an external crystal, and not by a different clock source. rstin 140 i reset input with cmos schmitt- trigger characteristics. a low level at this pin for a specified duration while the oscillator is running resets the st10f276. an internal pull-up resistor permits power-on reset using only a capacitor connected to v ss . in bidirectional reset mode (enabled by setting bit bdrsten in syscon register), the rstin line is pulled low for the duration of the internal reset sequence. rstout 141 o internal reset indication output. this pin is driven to a low level during hardware, software or watchdog timer reset. rstout remains low until the einit (end of initialization) in struction is executed. nmi 142 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. if bit pwdcfg = ?0? in syscon register, when the pwrdn (power down) instru ction is executed, the nmi pin must be low in order to force the st10f276 to go into power down mode. if nmi is high and pwdcfg =?0?, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. v aref 37 - a/d converter reference voltage and analog supply v agnd 38 - a/d converter reference and analog ground rpd 84 - timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection. v dd 17, 46, 72,82,93, 109, 126, 136 - digital supply voltage = + 5v during normal operation, idle and power down modes. it can be turned off when stand-by ram mode is selected. v ss 18,45, 55,71, 83,94, 110, 127, 139 - digital ground v 18 56 - 1.8v decoupling pin: a decoupling capacit or (typical value of 10nf, max 100nf) must be connected between this pin and nearest v ss pin. table 1. pin description (continued) symbol pin type function
st10f276 functional description 23/229 3 functional description the architecture of the st10f276 combines advantages of both risc and cisc processors and an advanced perip heral subsystem. the block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the st10f276. figure 3. block diagram external bus controller 10-bit adc gpt1 / gpt2 asc0 brg brg ssc0 pwm capcom2 capcom1 por t 0 port 1 port 4 port 6 port 5 cpu-core and mac unit xcan2 xssc xasc xcan1 xi2c xram 2k xram 16k xram 48k (stby) (pec) xflash 320k iflash 512k 32 16 16 16 16 16 16 16 16 16 16 16 pec interrupt controller port 3 port 7 por t 8 16 watchdog iram 2k 16 xrtc oscillator pll 5v-1.8v voltage regulator port 2 16 16 8 81615 8 8 16 16 32khz oscillator xpwm 16
internal flash memory st10f276 24/229 4 internal flash memory 4.1 overview the on-chip flash is composed by two matr ix modules each one containing one array divided in two banks that can be read and modified independently one of the other: one bank can be read while another bank is under modification. figure 4. flash modules structure the write operations of the 4 banks are managed by an embedded flash program/erase controller (fpec). the high voltages needed for program/erase operations are internally generated. the data bus is 32-bit wide. due to st10 core architecture limitation, only the first 512 kbytes are accessed at 32-bit (internal flash bus, see i-bus), while the remaining 320 kbytes are accessed at 16-bit (see x-bus). 4.2 functional description 4.2.1 structure the following table shows the address space reserved to the flash module. bank 1: 128 kbyte bank 0: 384 kbyte program memory hv and ref. generator program/erase controller i-bus interface + 8 kbyte test-flash bank 3: 128 kbyte bank 2: 192 kbyte program memory xflash (module x) x-bus interface iflash (module i) control section program memory program memory table 2. flash modules absolute mapping description addresses size iflash sectors 0x00 0000 to 0x08 ffff 512 kbyte xflash sectors 0x09 0000 to 0x0d ffff 320 kbyte registers and flash internal reserved area 0x0e 0000 to 0x0e ffff 64 kbyte
st10f276 internal flash memory 25/229 4.2.2 modules structure the iflash module is composed by 2 banks. bank 0 contains 384 kbyte of program memory divided in 10 sectors. bank 0 contains also a reserved sector named test-flash. bank 1 contains 128 kbyte of program memory or parameter divided in 2 sectors (64 kbyte each). the xflash module is composed by 2 banks as well. bank 2 contains 192 kbyte of program memory divided in 3 sectors. bank 3 contains 128 kbyte of program memory or parameter divided in 2 sectors (64 kbyte each). addresses from 0x0e 0000 to 0x0e ffff are reserved for the control register interface and other internal service memory space use d by the flash program/erase controller. the following tables show the memory mapping of the flash when it is accessed in read mode ( ta bl e 3 ), and when accessed in write or erase mode ( ta bl e 2 ): note that with this second mapping, the first three banks are remapped into code segment 1 (same as obtained when setting bit roms1 in syscon register). table 3. flash modules sectorization (read operations) bank description addresses size st10 bus size b0 bank 0 flash 0 (b0f0) 0x0000 0000 - 0x0000 1fff 8 kb 32-bit (i-bus) bank 0 flash 1 (b0f1) 0x0000 2000 - 0x0000 3fff 8 kb bank 0 flash 2 (b0f2) 0x0000 4000 - 0x0000 5fff 8 kb bank 0 flash 3 (b0f3) 0x0000 6000 - 0x0000 7fff 8 kb bank 0 flash 4 (b0f4) 0x0001 8000 - 0x0001 ffff 32 kb bank 0 flash 5 (b0f5) 0x0002 0000 - 0x0002 ffff 64 kb bank 0 flash 6 (b0f6) 0x0003 0000 - 0x0003 ffff 64 kb bank 0 flash 7 (b0f7) 0x0004 0000 - 0x0004 ffff 64 kb bank 0 flash 8 (b0f8) 0x0005 0000 - 0x0005 ffff 64 kb bank 0 flash 9 (b0f9) 0x0006 0000 - 0x0006 ffff 64 kb b1 bank 1 flash 0 (b1f0) 0x0007 0000 - 0x0007 ffff 64 kb bank 1 flash 1 (b1f1) 0x0008 0000 - 0x0008 ffff 64 kb b2 bank 2 flash 0 (b2f0) 0x0009 0000 - 0x0009 ffff 64 kb 16-bit (x-bus) bank 2 flash 1 (b2f1) 0x000a 0000 - 0x000a ffff 64 kb bank 2 flash 2 (b2f2) 0x000b 0000 - 0x000b ffff 64 kb b3 bank 3 flash 0 (b3f0) 0x000c 0000 - 0x000c ffff 64 kb bank 3 flash 1 (b3f1) 0x000d 0000 - 0x000d ffff 64 kb
internal flash memory st10f276 26/229 the table above refers to the configuration when bit roms1 of syscon register is set. when bootstrap mode is entered: ? test-flash is seen and available for code fetches (address 00?0000h) ? user iflash is only available for read and write accesses ? write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever roms1 bit in syscon value ? read accesses are made in segment 0 or in segment 1 depending of roms1 value. in bootstrap mode, by default roms1 = 0, so the first 32kbytes of iflash are mapped in segment 0. example: in default configuration, to program address 0, user must put the value 01'0000h in the farl and farh registers, but to verify the content of the address 0 a read to 00'0000h must be performed. table 5 shows the control register interface composition: this set of registers can be addressed by the cpu. table 4. flash modules sectorization (write operations or with roms1=?1?) bank description addresses size st10 bus size b0 bank 0 test-flash (b0tf) 0x0000 0000 - 0x0000 1fff 8 kb 32-bit (i-bus) bank 0 flash 0 (b0f0) 0x0001 0000 - 0x0001 1fff 8 kb bank 0 flash 1 (b0f1) 0x0001 2000 - 0x0001 3fff 8 kb bank 0 flash 2 (b0f2) 0x0001 4000 - 0x0001 5fff 8 kb bank 0 flash 3 (b0f3) 0x0001 6000 - 0x0001 7fff 8 kb bank 0 flash 4 (b0f4) 0x0001 8000 - 0x0001 ffff 32 kb bank 0 flash 5 (b0f5) 0x0002 0000 - 0x0002 ffff 64 kb bank 0 flash 6 (b0f6) 0x0003 0000 - 0x0003 ffff 64 kb bank 0 flash 7 (b0f7) 0x0004 0000 - 0x0004 ffff 64 kb bank 0 flash 8 (b0f8) 0x0005 0000 - 0x0005 ffff 64 kb bank 0 flash 9 (b0f9) 0x0006 0000 - 0x0006 ffff 64 kb b1 bank 1 flash 0 (b1f0) 0x0007 0000 - 0x0007 ffff 64 kb bank 1 flash 1 (b1f1) 0x0008 0000 - 0x0008 ffff 64 kb b2 bank 2 flash 0 (b2f0) 0x0009 0000 - 0x0009 ffff 64 kb 16-bit (x-bus) bank 2 flash 1 (b2f1) 0x000a 0000 - 0x000a ffff 64 kb bank 2 flash 2 (b2f2) 0x000b 0000 - 0x000b ffff 64 kb b3 bank 3 flash 0 (b3f0) 0x000c 0000 - 0x000c ffff 64 kb bank 3 flash 1 (b3f1) 0x000d 0000 - 0x000d ffff 64 kb
st10f276 internal flash memory 27/229 4.2.3 low power mode the flash modules are automatically switched off executing pwrdn instruction. the consumption is drastically reduced, but exiting this state can require a long time (t pd ). note: recovery time from power down mode for the flash modules is anyway shorter than the main oscillator start-up time. to avoid any problem in restarting to fetch code from the flash, it is important to size properly the external circuit on rpd pin. power-off flash mode is entered only at the end of the eventually running flash write operation. 4.3 write operation the flash modules have one single register interface mapped in the memory space of the xflash module (0x0e 0000 to 0x0e 0013). all the operations are enabled through four 16-bit control registers: flash control register 1-0 high/low (fcr1h/l-fcr0h/l). eight other 16- bit registers are used to store flash address and data for program operations (farh/l and fdr1h/l-fdr0h/l) and write operation error flags (ferh/l). all registers are accessible with 8 and 16-bit instructions (since mapped on st10 xbus). note: before accessing the xflash module (and consequently also the flash register to be used for program/erasing operatio ns), bit xflashen in xpercon register and bit xpen in syscon register shall be set. the 4 banks have their own dedicated sense amplifiers, so that any bank can be read while any other bank is written. however simultaneo us write operations (?write? means either program or erase) on different banks are forbidden: when there is a write operation on going (program or erase) anywhere in the flash, no other write operation can be performed. during a flash write operation any attempt to read the bank unde r modification will output invalid data (software trap 009bh). this means that the flash bank is not fetchable when a write operation is active: the write operation commands must be executed from another table 5. control register interface bank description addresses size st10 bus size fcr1-0 flash control registers 1-0 0x000e 0000 - 0x000e 0007 8 byte 16-bit (x-bus) fdr1-0 flash data registers 1-0 0x000e 0008 - 0x000e 000f 8 byte far flash address registers 0x000e 0010 - 0x000e 0013 4 byte fer flash error register 0x000e 0014 - 0x000e 0015 2 byte fnvwpxr flash non volatile protection x register 0x000e dfb0 - 0x000e dfb3 4 byte fnvwpir flash non volatile protection i register 0x000e dfb4 - 0x000e dfb7 4 byte fnvapr0 flash non volatile access protection register 0 0x000e dfb8 - 0x000e dfb9 2 byte fnvapr1 flash non volatile access protection register 1 0x000e dfbc - 0x000e dfbf 4 byte xficr xflash interface control register 0x000e e000 - 0x000e e001 2 byte
internal flash memory st10f276 28/229 bank, or from the other module or again from another memory (internal ram or external memory). note: during a write operation, when bit lock of fcr0 is set, it is forbidden to write into the flash control registers. 4.3.1 power supply drop if during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the modules are reset to read mode. at following power-on, an interrupted flash write operation must be repeated. 4.4 registers description 4.4.1 flash control register 0 low the flash control register 0 low (fcr0l) together with the flash control register 0 high (fcr0h) is used to enable and to monitor all the write operations for both the flash modules. the user has no access in write mode to the test-flash (b0tf). besides, test- flash block is seen by the user in bootstrap mode only. fcr0l (0x0e 0000) fcr reset value: 0000h 1514131211109876543210 reserved bsy1 bsy0 lock res. bsy3 bsy2 res. rrr rr table 6. flash control register 0 low bit function bsy(3:2) bank 3:2 busy (xflash) these bits indicate that a write operation is running on the corresponding bank of xflash. they are automatically set when bit wms is set. setting protection operation sets bit bsy2 (since protection registers are in the block b2). when these bits are set every read access to the corresponding bank will output invalid data (software trap 009bh), while every write access to the bank will be ignored. at the end of the write operation or during a program or erase suspend these bits are automatically reset and the bank returns to read mode. after a program or erase resume these bits are automatically set again.
st10f276 internal flash memory 29/229 4.4.2 flash contro l register 0 high the flash control register 0 high (fcr0h) together with the flash control register 0 low (fcr0l) is used to enable and to monitor all the write operations for both the flash modules. the user has no access in write mode to the test-flash (b0tf). besides, test- flash block is seen by the user in bootstrap mode only. lock flash registers access locked when this bit is set, it means that the access to the flash control registers fcr0h/- fcr1h/l, fdr0h/l-fdr1h/l, farh/l and fer is locked by the fpec: any read access to the registers will output invalid data (software trap 009bh) and any write access will be ineffective. lock bit is autom atically set when the flash bit wms is set. this is the only bit the user can always acce ss to detect the status of the flash: once it is found low, the rest of fcr0l and all the other flash registers are accessible by the user as well. note that fer content can be read when lock is low, but its content is updated only when also bsy bits are reset. bsy(1:0) bank 1:0 busy (iflash) these bits indicate that a write operati on is running in the corresponding bank of iflash. they are automatically set when bit wms is set. when these bits are set every read access to the corresponding bank will output invalid data (software trap 009bh), while every write access to the bank will be ignored. at the end of the write operation or during a program or erase su spend these bits are automatically reset and the bank returns to read mode. after a program or erase resume these bits are automatically set again. table 6. flash control register 0 low (continued) bit function fcr0h (0x0e 0002) fcr reset value: 0000h 1514131211109876543210 wms susp wpg dwpg ser reserved spr smod reserved rw rw rw rw rw rw rw table 7. flash control register 0 high bit function smod select module if this bit is reset, the write operation is performed on xflash module; if this bit is set, the write operation is performed on iflash module. smod bit is automatically reset at the end of the write operation. spr set protection this bit must be set to select the set protection operation. the set protection operation allows to program 0s in place of 1s in the flash non volatile protection registers. the flash address in which to program must be written in the farh/l registers, while the flash data to be pr ogrammed must be written in the fdr0h/l before starting the execution by setting bit wms. a sequence error is flagged by bit seqer of fer if the address written in farh/l is not in the range 0x0edfb0- 0x0edfbf. spr bit is automatically reset at the end of the set protection operation.
internal flash memory st10f276 30/229 ser sector erase this bit must be set to select the sector erase operation in the flash modules. the sector erase operation allows to erase all the flash locations to 0xff. from 1 to all the sectors of the same bank (excluded test-flash for bank b0) can be selected to be erased through bits bxfy of fcr1h/l register s before starting the execution by setting bit wms. it is not necessary to pre-progra m the sectors to 0x00, because this is done automatically. ser bit is automatically rese t at the end of the sector erase operation. dwpg double word program this bit must be set to select the double word (64 bits) program operation in the flash modules. the double word program operation allows to program 0s in place of 1s. the flash address in which to program (aligned with even words) must be written in the farh/l registers, while the 2 flash data to be programmed must be written in the fdr0h/l registers (even word) and fdr1h/l registers (odd word) before starting the execution by setting bit wms. dwpg bit is automatically reset at the end of the double word program operation. wpg word program this bit must be set to select the word (32 bits) program operation in the flash modules. the word program operation allows to program 0s in place of 1s. the flash address to be programmed must be written in the farh/l registers, while the flash data to be programmed must be written in the fdr0h/l registers before starting the execution by setting bit wms. wpg bit is automatically reset at the end of the word program operation. susp suspend this bit must be set to suspend the current program (word or double word) or sector erase operation in order to read data in one of the sectors of the bank under modification or to program data in another bank. the suspend operation resets the flash bank to normal read mode (autom atically resetting bits bsyx). when in program suspend, the two flash modules accept only the following operations: read and program resume. when in erase suspend the modules accept only the following operations: read, erase resume and program (word or double word; program operations cannot be suspended during erase suspend). to resume the suspended operation, the wms bit must be set agai n, together with the selection bit corresponding to the operation to resume (wpg, dwpg, ser). note: it is forbidden to start a new write operation with bit susp already set. wms write mode start this bit must be set to start every write operation in the flash modules. at the end of the write operation or during a suspend, this bit is automatically reset. to resume a suspended operation, this bit must be set again. it is forbidden to set this bit if bit err of fer is high (the operation is not accepted ). it is also forbidden to start a new write (program or erase) operation (by setting wms high) when bit susp of fcr0 is high. resetting this bit by software has no effect. table 7. flash control register 0 high (continued) bit function
st10f276 internal flash memory 31/229 4.4.3 flash control register 1 low the flash control register 1 low (fcr1l), together with flash control register 1 high (fcr1h), is used to select the sectors to erase, or during any write operation to monitor the status of each sector of the module selected by smod bit of fcr0h. first diagram shows fcr1l meaning when smod=0; the second one when smod=1. fcr1l (0x0e 0004) smod=0 fcr reset value: 0000h 1514131211109876543210 reserved b2f2 b2f1 b2f0 rs rs rs fcr1l (0x0e 0004) smod=1 fcr reset value: 0000h 1514131211109876543210 reserved b0f9 b0f8 b0f7 b0f6 b0f5 b0f4 b0f3 b0f2 b0f1 b0f0 rs rs rs rs rs rs rs rs rs rs table 8. flash control register 1 low bit function smod=0 (xflash selected) b2f(2:0) bank 2 xflash sector 2:0 status these bits must be set during a sector erase operation to select the sectors to erase in bank 2. besides, during any erase operation, these bits are automatically set and give the status of the 3 sectors of bank 2 (b2f2-b2f0). the meaning of b2fy bit for sector y of bank 2 is given by the next ta ble 10. these bits are automatically reset at the end of a write operation if no errors are detected. smod=1 (iflash selected) b0f(9:0) bank 0 iflash sector 9:0 status these bits must be set during a sector erase operation to select the sectors to erase in bank 0. besides, during any erase operation, these bits are automatically set and give the status of the 10 sectors of bank 0 (b0f9-b0f0). the meaning of b0fy bit for sector y of bank 0 is given by the next ta b l e 1 0 . these bits are autom atically reset at the end of a write operation if no errors are detected.
internal flash memory st10f276 32/229 4.4.4 flash contro l register 1 high the flash control register 1 high (fcr1h), together with flash control register 1 low (fcr1l), is used to select the sectors to erase, or during any write operation to monitor the status of each sector and each bank of the module selected by smod bit of fcr0h. first diagram shows fcr1h meaning when smod=0; the second one when smod=1. during any erase operation, these bits are automatically set and give the status of the 2 sectors of bank 1 (b1f1-b1f0). the meaning of b1fy bit for sector y of bank 1 is given by the next ta bl e 1 0 . these bits are automatically reset at the end of a erase operation if no errors are detected. fcr1h (0x0e 0006) smod=0 fcr reset value: 0000h 1514131211109876543210 reserved b3s b2s reserved b3f1 b3f0 rs rs rs rs fcr1h (0x0e 0006) smod=1 fcr reset value: 0000h 1514131211109876543210 reserved b1s b0s reserved b1f1 b1f0 - rsrs rsrs table 9. flash control register 1 high bit function smod=0 (xflash selected) b3f(1:0) bank 3 xflash sector 1:0 status during any erase operation, these bits are au tomatically set and give the status of the 2 sectors of bank 3 (b3f1-b3f0). the meanin g of b3fy bit for sector y of bank 1 is given by the next ta bl e 1 0 . these bits are automatically reset at the end of a erase operation if no errors are detected. b(3:2)s bank 3-2 status (xflash) during any erase operation, these bits are automatically modified and give the status of the 2 banks (b3-b2). the meaning of bxs bit for bank x is given in the next ta bl e 1 0 . these bits are automatically reset at the end of a erase operation if no errors are detected. smod=1 (iflash selected) b1f(1:0) bank 1 iflash sector 1:0 status during any erase operation, these bits are au tomatically set and give the status of the 2 sectors of bank 1 (b1f1-b1f0). the meanin g of b1fy bit for sector y of bank 1 is given by the next table 10. these bits are automatically reset at the end of a erase operation if no errors are detected. b(1:0)s bank 1-0 status (iflash) during any erase operation, these bits are automatically modified and give the status of the 2 banks (b1-b0). the meaning of bxs bit for bank x is given in the next ta bl e 1 0 . these bits are automatically reset at the end of a erase operation if no errors are detected.
st10f276 internal flash memory 33/229 4.4.5 flash data register 0 low the flash address registers (farh/l) and the flash data registers (fdr1h/l-fdr0h/l) are used during the program operations to store flash address in which to program and data to program. 4.4.6 flash data register 0 high 4.4.7 flash data register 1 low table 10. banks (bxs) and sectors (bxfy) status bits meaning err susp bxs = 1 meaning bxfy = 1 meaning 1 - erase error in bank x erase error in sector y of bank x 0 1 erase suspended in bank x erase suspended in sector y of bank x 0 0 don?t care don?t care fdr0l (0x0e 0008) fcr reset value: ffffh 1514131211109876543210 din15 din14 din13 din12 din11 din10 din9 di n8 din7 din6 din5 din4 din3 din2 din1 din0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 11. flash data register 0 low bit function din(15:0) data input 15:0 these bits must be writt en with the data to program the flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. fdr0h (0x0e 000a) fcr reset value: ffffh 1514131211109876543210 din31 din30 din29 din28 din27 din26 din25 din24 din23 din22 din21 din20 din19 din18 din17 din16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 12. flash data register 0 high bit function din(31:16) data input 31:16 these bits must be writt en with the data to program the flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. fdr1l (0x0e 000c) fcr reset value: ffffh 1514131211109876543210 din15 din14 din13 din12 din11 din10 din9 di n8 din7 din6 din5 din4 din3 din2 din1 din0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
internal flash memory st10f276 34/229 4.4.8 flash data register 1 high 4.4.9 flash address register low table 13. flash data register 1 low bit function din(15:0) data input 15:0 these bits must be written with the data to program the flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. fdr1h (0x0e 000e) fcr reset value: ffffh 1514131211109876543210 din31 din30 din29 din28 din27 din26 din25 din24 din23 din22 din21 din20 din19 din18 din17 din16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 14. flash data register 1 high bit function din( 31:16 ) data input 31:16 these bits must be writt en with the data to program the flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. farl (0x0e 0010) fcr reset value: 0000h 1514131211109876543210 add15 add14 add13 add12 add11 add10 add9 add8 add7 add6 add5 add4 add3 add2 reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 15. flash address register low bit function add(15:2) address 15:2 these bits must be written with the address of the flash location to program in the following operations: word program (32-bit) and double word program (64-bit). in double word program bit add2 must be written to ?0?.
st10f276 internal flash memory 35/229 4.4.10 flash addr ess register high 4.4.11 flash error register flash error register, as well as all the other fl ash registers, can be properly read only once lock bit of register fcr0l is low. nevertheless, its content is updated when also bsy bits are reset as well; for this reason, it is definitively meaningful reading fer register content only when lock bit and all bsy bits are cleared. farh (0x0e 0012) fcr reset value: 0000h 1514131211109876543210 reserved add20 add19 add18 add17 add16 rw rw rw rw rw table 16. flash address register high bit function add(20:16) address 20:16 these bits must be written with the address of the flash location to program in the following operations: word program and double word program. fer (0xe 0014h) fcr reset value: 0000h 1514131211109876543210 reserved wpf reser seqer reserved 10er pger erer err rc rc rc rc rc rc rc table 17. flash error register bit function err write error this bit is automatically set when an error occurs during a flash write operation or when a bad write operation setup is done. once the error has been discovered and understood, err bit must be software reset. erer erase error this bit is automatically set when an erase error occurs during a flash write operation. this error is due to a real failure of a flas h cell, that can no more be erased. this kind of error is fatal and the sector where it occurred must be discarded. this bit has to be software reset. pger program error this bit is automatically set when a program error occurs during a flash write operation. this error is due to a real failure of a flash cell, that can no more be programmed. the word where this error occurred must be discarded. this bit has to be software reset. 10er 1 over 0 error this bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the protection bits). this error is not due to a failure of the flash cell, but only flags that the desired data has not been written. this bit has to be software reset.
internal flash memory st10f276 36/229 4.4.12 xflash inte rface control register this register is used to configure the xflash interface behaviour on the xbus. it allows to set the number of wait states introduced on the xbus before the internal ready signal is given to the st10 bus master. seqer sequence error this bit is automatically set when the co ntrol registers (fcr1h/l-fcr0h/l, farh/l, fdr1h/l-fdr0h/l) are not correctly filled to execute a valid write operation. in this case no write operation is executed. this bit has to be software reset. reser resume error this bit is automatically set when a su spended program or erase operation is not resumed correctly due to a protocol error. in this case the suspended operation is aborted. this bit has to be software reset. wpf write protection flag this bit is automatically set when trying to program or erase in a sector write protected. in case of multiple sector eras e, the not protected sectors are erased, while the protected sectors are not erased and bit wpf is set. this bit has to be software reset. table 17. flash error register (continued) bit function xficr (0xe e000h) xbus reset value: 000fh 1514131211109876543210 reserved ws3 ws2 ws1 ws0 rw rw rw rw table 18. xflash interface control register bit function ws(3:0) wait state setting these three bits are the binary coding of th e number of wait states introduced by the xflash interface through the xbus internal ready signal. default value after reset is 1111, that is the up to 15 wait states are set. the following recommendations for the st10f276 are hereafter reported: for f cpu > 40mhz1 wait-statews(3:0) = ?0001? for f cpu 40mhz0 wait-statews(3:0) = ?0000?
st10f276 internal flash memory 37/229 4.5 protection strategy the protection bits are stored in non volatile flash cells inside xflash module, that are read once at reset and stored in 7 volatile registers. before they are read from the non volatile cells, all the available protections are forced active during reset. the protections can be programmed using the set protection operation (see flash control registers paragraph), that can be executed from all the internal or external memories except from the flash bank b2. two kind of protections are available: write protections to avoid unwanted writings and access protections to avoid piracy. in next paragraphs all different level of protections are shown, and architecture limitations are highlighted as well. 4.5.1 protection registers the 7 non volatile protection registers are one time programmable for the user. four registers (fnvwpxrl/h-fnvwpirl/h) are used to store the write protection fuses respectively for each sector of the xflash module (see x) and iflash module (see i). the other three registers (fnvapr0 and fnvapr1l/h) are used to store the access protection fuses (common to both flash modules even though with some limitations). 4.5.2 flash non volatile writ e protection x register low fnvwpxrl (0x0e dfb0) nvr delivery value: ffffh 1514131211109876543210 w2ppr reserved w2p2w2p1w2p0 rw rw rw rw table 19. flash non volatile write protection x register low bit function w2p(2:0) write protection bank 2 sectors 2-0 (xflash) these bits, if programmed at 0, disable any write access to the sectors of bank 2 (xflash). w2ppr write protection bank 2 non volatile cells this bit, if programmed at 0, disables any wr ite access to the non volatile cells of bank 2. since these non volatile cells are dedicated to protection registers, once w2ppr bit is set, the configuration of protection setting is frozen, and can only be modified executing a temporary writ e unprotection operation.
internal flash memory st10f276 38/229 4.5.3 flash non volatile writ e protection x register high 4.5.4 flash non volatile writ e protection i register low 4.5.5 flash non volatile writ e protection i register high fnvwpxrh (0x0e df b2) nvr delivery value: ffffh 1514131211109876543210 reserved w3p1w3p0 rw rw table 20. flash non volatile write protection x register high bit function w3p(1:0) write protection bank 3 / sectors 1-0 (xflash) these bits, if programmed at 0, disable any write access to the sectors of bank 3 (xflash). fnvwpirl (0x0e dfb4) n vr delivery value: ffffh 1514131211109876543210 reserved w0p9w0p8w0p7w0p6 w0p5w0p4w0p3w0p2w0p1w0p0 rw rw rw rw rw rw rw rw rw rw table 21. flash non volatile write protection i register low bit function w0p(9:0) write protection bank 0 / sectors 9-0 (iflash) these bits, if programmed at 0, disable any write access to the sectors of bank 0 (iflash). fnvwpirh (0x0e dfb6) nvr delivery value: ffffh 1514131211109876543210 reserved w1p1w1p0 rw rw table 22. flash non volatile write protection i register high bit function w1p(1:0) write protection bank 1 / sectors 1-0 (iflash) these bits, if programmed at 0, disable any write access to the sectors of bank 1 (iflash).
st10f276 internal flash memory 39/229 4.5.6 flash non volatile acces s protection register 0 due to st10 architecture, the xflash is seen as external memory: this made impossible to access protect it from real external memory or internal ram. 4.5.7 flash non volatile access protection register 1 low fnvapr0 (0x0e dfb8) nvr delivery value: acffh 1514131211109876543210 reserved dbgp accp rw rw table 23. flash non volatile access protection register 0 bit function accp access protection this bit, if programmed at 0, disables an y access (read/write) to data mapped inside iflash module address space, unless the current instruction is fetched from one of the two flash modules. dbgp debug protection this bit, if erased at 1, allows to by-pass all the protections using the debug features through the test interface. if programmed at 0, on the contrary, all the debug features, the test interface and all the flash test modes are disabled. even stmicroelectronics will not be able to access the device to run any eventual failure analysis. fnvapr1l (0x0e dfbc) nvr delivery value: ffffh 1514131211109876543210 pds15 pds14 pds13 pds12 pds11 pds10 pds9 pds8 pds7 pds6 pds5 pds4 pds3 pds2 pds1 pds0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 24. flash non volatile access protection register 1 low bit function pds(15:0) protections disable 15-0 if bit pdsx is programmed at 0 and bit penx is erased at 1, the action of bit accp is disabled. bit pds0 can be programmed at 0 on ly if bits dbgp and accp have already been programmed at 0. bit pdsx can be programmed at 0 only if bit penx-1 has already been programmed at 0.
internal flash memory st10f276 40/229 4.5.8 flash non volatile access protection register 1 high 4.5.9 access protection the flash modules have one level of access protection (access to data both in reading and writing): if bit accp of fnvapr0 is programmed at 0, the iflash module become access protected: data in the iflash module can be read/written only if the current execution is from the iflash module itself. protection can be permanently disabled by programming bit pds0 of fnvapr1h, in order to analyze rejects. allowing pds0 bit programming only when accp bit is programmed, guarantees that only an execution from the flash itself can disable the protections. protection can be permanently enabled again by programming bit pen0 of fnvapr1l. the action to disable and enable again access protections in a permanent way can be executed a maximum of 16 times. trying to write into the access protected fl ash from internal ram will be unsuccessful. trying to read into th e access protected flash from inte rnal ram will output a dummy data. when the flash module is protected in access, also the data access through pec of a peripheral is forbidden. to read/write data in pec mode from/to a protected bank, first it is necessary to temporary unprotect the flash module. due to st10 architecture, the xflash is seen as external memory: this makes impossible to access protect it from real external memory or internal ram. in the following table a summary of all levels of possible access protection is reported: in particular, supposing to enable all possible access protections, when fetching from a memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table. fnvapr1h (0x0e dfbe) nvr d elivery value: ffffh 1514131211109876543210 pen15 pen14 pen13 pen12 pen11 pen10 pen9 pen8 pen7 pen6 pen5 pen4 pen3 pen2 pen1 pen0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 25. flash non volatile access protection register 1 high bit function pen15-0 protections enable 15-0 if bit penx is programmed at 0 and bit pdsx+1 is erased at 1, the action of bit accp is enabled again. bit penx can be programmed at 0 only if bit pdsx has already been programmed at 0. table 26. summary of access protection level read iflash / jump to iflash read xflash /jump to xflash read flash registers write flash registers fetching from iflash yes / yes yes / yes yes yes fetching from xflash no / yes yes / yes yes no fetching from iram no / yes yes / yes yes no
st10f276 internal flash memory 41/229 4.5.10 write protection the flash modules have one level of write protections: each sector of each bank of each flash module can be software write protected by programming at 0 the related bit wypx of fnvwpxrh/l-fnvwpirh/l registers. 4.5.11 temporar y unprotection bits wypx of fnvwpxrh/l-fnvwpirh/l can be temporary unprotected by executing the set protection operation and writing 1 into these bits. bit accp can be temporary unprotected by executing the set protection operation and writing 1 into these bits, but only if these write instructions are executed from the flash modules. to restore the write and access protection bits it is necessary to reset the microcontroller or to execute a set protection operation and write 0 into the desired bits. it is not necessary to temporary unprotect an access protected flash in order to update the code: it is, in fact, sufficient to execute the updating instructions from another flash bank. in reality, when a temporary unprotection operation is executed, the corresponding volatile register is written to 1, while the non volatile registers bits previously written to 0 (for a protection set operation), will cont inue to maintain the 0. for th is reason, the user software must be in charge to track the current protection status (for instance using a specific ram area), it is not possible to deduce it by reading the non volatile register content (a temporary unprotection cannot be detected). fetching from xram no / yes yes / yes yes no fetching from external memory n o / ye s ye s / ye s ye s n o table 26. summary of access protection level read iflash / jump to iflash read xflash /jump to xflash read flash registers write flash registers
internal flash memory st10f276 42/229 4.6 write operation examples in the following, examples for each kind of flash write operation are presented. word program example: 32-bit word prog ram of data 0xaaaaaaaa at addre ss 0x0c5554 in xflash module. fcr0h|= 0x2000; /*set wpg in fcr0h*/ farl = 0x5554; /*load add in farl*/ farh = 0x000c; /*load add in farh*/ fdr0l = 0xaaaa; /*load data in fdr0l*/ fdr0h = 0xaaaa; /*load data in fdr0h*/ fcr0h|= 0x8000; /*operation start*/ double word program example: double word program (64-bit) of data 0x55aa55aa at address 0x095558 and data 0xaa55aa55 at address 0x09555c in iflash module. fcr0h|= 0x1080; /*set dwpg, smod*/ farl = 0x5558; /*load add in farl*/ farh = 0x0009; /*load add in farh*/ fdr0l = 0x55aa; /*load data in fdr0l*/ fdr0h = 0x55aa; /*load data in fdr0h*/ fdr1l = 0xaa55; /*load data in fdr1l*/ fdr1h = 0xaa55; /*load data in fdr1h*/ fcr0h|= 0x8000; /*operation start*/ double word program is always performed on the double word aligned on a even word: bit add2 of farl is ignored. sector erase example: sector erase of sectors b3f1 and b3f0 of bank 3 in xflash module. fcr0h|= 0x0800; /*set ser in fcr0h*/ fcr1h|= 0x0003; /*set b3f1, b3f0*/ fcr0h|= 0x8000; /*operation start*/ suspend and resume word program, double word program, and sector erase operations can be suspended in the following way: fcr0h|= 0x4000; /*set susp in fcr0h*/ then the operation can be resumed in the following way: fcr0h|= 0x0800; /*set ser in fcr0h*/ fcr0h|= 0x8000; /*operation resume*/ before resuming a suspended erase, fcr1h/fcr1l must be read to check if the erase is already completed (fcr1h = fcr1l = 0x0000 if erase is complete). original setup of select operation bits in fcr0h/l must be restored before the operation resume, otherwise the operation is aborted an d bit reser of fer is set.
st10f276 internal flash memory 43/229 erase suspend, program and resume a sector erase operation can be suspended in order to program (word or double word) another sector. example: sector erase of sector b3f1 of bank 3 in xflash module. fcr0h|= 0x0800;/*set ser in fcr0h*/ fcr1h|= 0x0002;/*set b3f1*/ fcr0h|= 0x8000;/*operation start*/ example: sector erase suspend. fcr0h|= 0x4000;/*set susp in fcr0h*/ do /*loop to wait for lock=0 and wms=0*/ {tmp1 = fcr0l; tmp2 = fcr0h; } while ((tmp1 && 0x0010) || (tmp2 && 0x8000)); example: word program of data 0x5555aaaa at address 0x0c5554 in xflash module. fcr0h&= 0xbfff;/*rst susp in fcr0h*/ fcr0h|= 0x2000;/*set wpg in fcr0h*/ farl = 0x5554; /*load add in farl*/ farh = 0x000c; /*load add in farh*/ fdr0l = 0xaaaa; /*load data in fdr0l*/ fdr0h = 0x5555; /*load data in fdr0h*/ fcr0h|= 0x8000; /*operation start*/ once the program operation is finished, the erase operation can be resumed in the following way: fcr0h|= 0x0800;/*set ser in fcr0h*/ fcr0h|= 0x8000;/*operation resume*/ notice that during the program operation in erase suspend, bits ser and susp are low. a word or double word program during erase suspend cannot be suspended. to summarize: ? a sector erase can be suspended by setting susp bit ? to perform a word program operation during erase suspend, firstly bits susp and ser must be reset, then bit wpg and wms can be set ? to resume the sector erase operation bit ser must be set again ? in any case it is forbidden to start any write operation with susp bit already set set protection example 1: enable write protection of sectors b0f3-0 of bank 0 in iflash module. fcr0h|= 0x0100;/*set spr in fcr0h*/ farl = 0xdfb4;/*load add of register fnvwpirl in farl*/ farh = 0x000e;/*load add of register fnvwpirl in farh*/ fdr0l = 0xfff0;/*load data in fdr0l*/ fdr0h = 0xffff;/*load data in fdr0h*/ fcr0h|= 0x8000;/*operation start*/ notice that bit smod of fcr0h must not be set, since write protection bits of iflash module are stored in test-flash (xflash module).
internal flash memory st10f276 44/229 example 2: enable access and debug protection. fcr0h|= 0x0100;/*set spr in fcr0h*/ farl = 0xdfb8;/*load add of register fnvapr0 in farl*/ farh = 0x000e;/*load add of register fnvapr0 in farh*/ fdr0l = 0xfffc;/*load data in fdr0l*/ fcr0h|= 0x8000;/*operation start*/ example 3: disable in a permanent way access and debug protection. fcr0h|= 0x0100;/*set spr in fcr0h*/ farl = 0xdfbc;/*load add of register fnvapr1l in farl*/ farh = 0x000e;/*load add of register fnvapr1l in farh*/ fdr0l = 0xfffe; /*load data in fdr0l for clearing pds0*/ fcr0h|= 0x8000;/*operation start*/ example 4: enable again in a permanent way access and debug protection, after having disabled them. fcr0h|= 0x0100;/*set spr in fcr0h*/ farl = 0xdfbc;/*load add register fnvapr1h in farl*/ farh = 0x000e;/*load add register fnvapr1h in farh*/ fdr0h = 0xfffe;/*load data in fdr0h for clearing pen0*/ fcr0h|= 0x8000;/*operation start*/ disable and re-enable of access and debug protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times. 4.7 write operation summary in general, each write operation is started through a sequence of 3 steps: 1. the first instruction is used to select the desired operation by setting its corresponding selection bit in the flash contro l register 0. this instructio n is also used to select in which flash module to apply the write operation (by setting/resetting bit smod). 2. the second step is the definition of the address and data for programming or the sectors or banks to erase. 3. the last instruction is used to start the write operation, by setting the start bit wms in the fcr0. once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. a summary of the available flash module write operations are shown in the following ta bl e 2 7 . table 27. flash write operations operation select bit add ress and data start bit word program (32-bit) wpg farl/farh fdr0l/fdr0h wms double word program (64-bit) dwpg farl/farh fdr0l/fdr0h fdr1l/fdr1h wms sector erase ser fcr1l/fcr1h wms
st10f276 internal flash memory 45/229 set protection spr fdr0l/fdr0h wms program/erase suspend susp none none table 27. flash write operations (continued) operation select bit add ress and data start bit
bootstrap loader st10f276 46/229 5 bootstrap loader st10f276 implements innovative boot capabilities in order to - support a user defined bootstrap (see alternate bootstrap loader ); - support bootstrap via uart or bootstrap via can for the standard bootstrap. 5.1 selection among user-code, st andard or alternate bootstrap the selection among user-code, standard bootstrap or alternate bootstrap is made by special combinations on port0l[5...4] during the time the reset configuration is latched from port0. the alternate boot mode is triggered with a special combination set on port0l[5...4]. those signals, as other configuration signals, are latched on the rising edge of rstin pin. the alternate boot function is divided in two functional parts (which are independent from each other): part 1: selection of reset sequence according to the port0 configuration: user mode and alternate mode signatures decoding of reset configuration (p0l.5 = 1, p0l.4 = 1) selects the normal mode and the user flash to be mapped from address 00?0000h. decoding of reset configuration (p0l.5 = 1, p0l.4 = 0) selects st10 standard bootstrap mode (test-flash is active and overlaps us er flash for code fetches from address 00'0000h; user flash is active and available for read and program). decoding of reset configuration (p0l.5 = 0, p0l.4 = 1) activates new verifications to select which bootstrap software to execute: ? if the user mode signature in the user flash is programmed correctly, then a software reset sequence is selected and the user code is executed; ? if the user mode signature is not programmed correctly but the alternate mode signature in the user flash is programmed correctly, then the alternate boot mode is selected; ? if both the user and the alternate mode signatures are not programmed correctly in the user flash, then the user key location is read again. its value will determine the behavior of the selected bootstrap loader. part 2: running of user selected reset sequence standard bootstrap loader: jump to a predefined memory location in test-flash (controlled by st) alternate boot mode: jump to address 09?0000h selective bootstrap loader: jump to a predefined location in test-flash (controlled by st) and check which communication channel is selected user code: make a software reset and jump to 00?0000h
st10f276 bootstrap loader 47/229 5.2 standard bootstrap loader the built-in bootstrap loader of the st10f276 provides a mechanism to load the startup program, which is executed after reset, via the serial interface. in this case no external (rom) memory or an internal rom is required for the initialization code starting at location 00?0000 h . the bootstrap loader moves code/data into the iram but it is also possible to transfer data via the serial interface into an external ram using a second level loader routine. rom memory (internal or external) is not necessary. however, it may be used to provide lookup tables or may provide ?core-code?, that is, a set of general purpose subroutines, such as for i/o operations, number crunching or system initialization. the bootstrap loader can load the complete application software into romless systems, temporary software into complete systems for testing or calibration, a programming routine for flash devices. the bsl mechanism may be used for standard system start-up as well as for only special occasions like system maintenance (firmware update) or end-of- line programming or testing. 5.2.1 entering the st andard bootstrap loader as with the old st10 bootstrap mode, the st10f276 enters bsl mode if pin p0l.4 is sampled low at the end of a hardware reset. in this case, the built-in bootstrap loader is activated independently of the selected bus mode. the bootstrap loader code is stored in a special test-flash; no part of the standard flash memory area is required for this. after entering bsl mode and the respective initialization, the st10f276 scans the rxd0 line and the can1_rxd line to receive either a valid dominant bit from the can interface or a start condition from the uart line. start condition on uart rxd: the st10f276 starts the standard bootstrap loader. this bootstrap loader is identical to other st10 devices (examples: st10f269, st10f168). see paragraph 5.3 for details. valid dominant bit on can1 rxd: the st10f276 starts bootstrapping via can1; the bootstrapping method is new and is described in the next paragraph 5.4. the following figure 5 shows the program flow of the new bo otstrap loader. it clearly illustrates how the new functionalities are implemented: uart: uart has priority over can after a falling edge on can1_rxd until the first valid rising edge on can1_rxd; can: pulses on can1_rxd shorte r than 20*cpu-cycles are filtered. table 28. st10f276 boot mode selection p0.5 p0.4 st10 decoding 1 1 user mode: user flash mapped at 00?0000h 10 standard bootstrap loader: user flash mapped from 00?0000h; code fetches redirected to test-flash at 00?0000h 0 1 alternate boot mode: flash mapping depends on signatures integrity check 00reserved
bootstrap loader st10f276 48/229 5.2.2 st10 confi guration in bsl when the st10f276 has entered bsl mode, the configuration shown in ta bl e 2 9 is automatically set (values that deviate from the normal reset values are marked in bold ). table 29. st10 configuration in bsl mode function or register access notes watchdog timer disabled register syscon 0404 h (1) 1. in bootstrap modes (standard or alternate) romen, bit 10 of syscon, is always set regardless of ea pin level. bytdis, bit 9 of syscon, is set according to data bus width selection via port0 configuration. xpen bit set for bootstrap via can or alternate boot mode context pointer cp fa00 h register stkun fc00 h stack pointer sp fa40 h register stkov fa00 h register buscon0 acc. to startup config. (2) 2. buscon0 is initialized with 0000h, external bus disabled, if pin ea is high during reset. if pin ea is low during reset, busact0, bit 10, and alectl0, bit 9, are set enabling the external bus with lengthened ale signal. btyp field, bit 7 and 6, is set according to port0 configuration. register s0con 8011 h initialized only if bootstrap via uart register s0bg acc. to ?00? byte initialized only if bootstrap via uart p3.10 / txd0 ? 1 ? initialized only if bootstrap via uart dp3.10 ? 1 ? initialized only if bootstrap via uart can1 status/control register 0000 h initialized only if bootstrap via can can1 bit timing register acc. to ?0? fr ame initialized only if bootstrap via can xpercon 042d h xram1-2, xflash, can1 and xmisc enabled. initialized only if bootstrap via can p4.6 / can1_txd ? 1? initialized only if bootstrap via can dp4.6 ? 1? initialized only if bootstrap via can
st10f276 bootstrap loader 49/229 figure 5. st10f276 new standard bootstrap loader program flow other than after a normal reset the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. depending on the selected seri al link (uart0 or can1), pin txd0 or can1_txd is configured as output, so the st10f276 can return the acknowledge byte. even if the internal iflash is enabled, a code cannot be executed from it. start falling-edge on uart0 rxd? falling-edge on can1 rxd? start timer pt0 uart rxd = 0? can1 rxd = 1? pt0 > 20? no count = 1 can rxd = 0? no can1 rxd = 1? no count += 1 count = 5? stop timer pt0 initialize can address = fa40h no stop timer pt0 message received? no [address] = mo15_data0 address = address + 1 address = fac0h? no glitch on can1 rxd clear timer pt0 no no start timer t6 uart0 rxd = 1? no stop timer t6 initialize uart send acknowledge address = fa40h byte received? no [address] = s0rbuf address = address + 1 address = fa60h? no ye s jump to address fa40h uart boot can boot can boot uart boot no
bootstrap loader st10f276 50/229 5.2.3 booting steps as figure 6 shows, booting st10f276 with the boot loader code occurs in a minimum of four steps: 1. the st10f276 is reset with p0l.4 low. 2. the internal new bootstrap code runs on the st10 and a first level user code is downloaded from the external device, via the selected serial link (uart0 or can1). the bootstrap code is contained in the st10f276 test-flash and is automatically run when st10f276 is reset with p0l.4 low. after loading a preselected number of bytes, st10f276 begins executing the downloaded program. 3. the first level user code runs on st10f276. typically, this first level user code is another loader that downloads the application software into the st10f276. 4. the loaded application software is now running. figure 6. booting steps for st10f276 5.2.4 hardware to activate bsl the hardware that activates the bsl during reset may be a simple pull-down resistor on p0l.4 for systems that use this feature at every hardware reset. for systems that use the bootstrap loader only temporarily, it may be preferable to use a switchable solution (via jumper or an external signal). note: can alternate function on port4 lines is no t activated if the user has selected eight address segments (port4 pins have three functions: i/o port, address segment and can). boot via can requires that four or less address segments are selected. external device serial link external device serial link external device serial link external device serial link run bootstrap code run first level code run application code step 1 step 2 step 3 step 4 download first level user code download application entering bootstrap loading first level user code loading the application and exiting bsl st10f276 st10f276 st10f276 st10f276 from test-flash from dpram @ fa40h
st10f276 bootstrap loader 51/229 figure 7. hardware provisions to activate the bsl 5.2.5 memory configuration in bootstrap loader mode the configuration (t hat is, the accessibility) of the st10 f276?s memory areas after reset in bootstrap loader mode differs from the standard case. pin ea is evaluated when bsl mode is selected to enable or to not enable the external bus: if ea = 1, the external bus is disabled (busact0 = 0 in buscon0 register); if ea = 0, the external bus is enabled (busact0 = 1 in buscon0 register). moreover, while in bsl mode, accesses to the internal iflash area are partially redirected: all code accesses are made from the special test-flash seen in the range 00?0000h to 00?01fffh; user iflash is only available for read and write accesses (test-flash cannot be read or written); write accesses must be made with addresses starting in segment 1 from 01'0000h, regardless of the value of roms1 bit in syscon register; read accesses are made in segment 0 or in segment 1 depending on the roms1 value; in bsl mode, by default, roms1 = 0, so the first 32 kbytes of iflash are mapped in segment 0. example: in default configuration, to program address 0, the user must put the value 01'0000h in the farl and farh registers but to verify the content of the address 0 a read to 00'0000h must be performed. r p0l.4 8k ? max. circuit 1 p0l.4 p0l.4 normal boot bsl external signal r p0l.4 8k ? max. circuit 2
bootstrap loader st10f276 52/229 note: as long as st10f276 is in bsl, the user?s software should not try to execute code from the internal iflash, as the fetches are redirected to the test-flash. 5.2.6 loading the start-up code after the serial link initialization sequence (see following chapters), the bsl enters a loop to receive 32 bytes (boot via uart) or 128 bytes (boot via can). these bytes are stored sequentially into st10f276 dual-port ram from location 00?fa40h. to execute the loaded code, the bsl then jumps to location 00?fa40h. the bootstrap sequence running from the test-flash is now terminated; however, the microcontroller remains in bsl mode. most probably, the initially loa ded routine, being the first leve l user code, will load additional code and data. this first level user code may use the pre-initialized interface (uart or can) to receive data and a second level of code, and store it in arbitrary user-defined locations. this second level of code may be the final application code another, more sophisticated, loader routin e that adds a transmission protocol to enhance the integrity of the loaded code or data a code sequence to change the system configuration and enable the bus interface to store the received data into external memory in all cases, the st10f276 st ill runs in bsl mode, that is, with the watchdog timer disabled and limited access to the internal iflash area. figure 8. memory configuration after reset 16 mbytes 16 mbytes 16 mbytes bsl mode active yes (p0l.4 = ?0?) yes (p0l.4 = ?0?) no (p0l.4 = ?1?) ea pin high low according to application code fetch from internal flash area test-flash access test-flash access user iflash access data fetch from internal flash area user iflash access user ifl ash access user iflash access int. flash enabled test-flash user flash access to external bus disabled access to int. ram 1 0 255 int. flash enabled test-flash user flash access to external bus enabled access to int. ram 1 0 255 depends on reset config. user flash int. ram 255 1 0 depends on reset config. (ea , p0)
st10f276 bootstrap loader 53/229 5.2.7 exiting bootstrap loader mode to execute a program in normal mode, the bsl mode must first be terminated . the st10f276 exits bsl mode at a software reset (level on p0l.4 is ignored) or a hardware reset (p0l.4 must be high in this case). after the reset, the st10f276 starts executing from location 00?0000 h of the internal flash (user flash) or the external memory, as programmed via pin ea . note: if a bidirectional software reset is executed and external memory boot is selected (ea =0), a degeneration of the software reset event into a hardware reset can occur (refer to section for details). this implies that p0l.4 becomes transparent, so to exit from bootstrap mode it would be necessary to release pin p0l.4 (it is no longer ignored). 5.2.8 hardware requirements although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements relative to the new bootstrap loader: ? external bus configuration: must have four or less segment address lines (keep can i/os available); ? usage of can pins (p4.5 and p4.6): even in bootstrap via uart, p4.5 (can1_rxd) can be used as port input but not as output. the pin p4.6 (can1_txd) can be used as input or output. ? level on uart rxd and can1_rxd during the bootstrap phase (see figure 6 - step 2): must be 1 (external pull-ups recommended). 5.3 standard bootstrap with uart (rs232 or k-line) 5.3.1 features st10f276 bootstrap via uart has the same overall behavior as the old st10 bootstrap via uart: same bootstrapping steps; same bootstrap method: analyze the timing of a predefined byte, send back an acknowledge byte, load a fixed number of bytes and run; same functionalities: boot with different crystals and pll ratios.
bootstrap loader st10f276 54/229 figure 9. uart bootstrap loader sequence 5.3.2 entering bootstrap via uart the st10f276 enters bsl mode if pin p0l.4 is sampled low at the end of a hardware reset. in this case, the built-in bootstrap loader is activated independently of the selected bus mode. the bootstrap loader code is stored in a special test-flash; no part of the standard mask rom or flash memory area is required for this. after entering bsl mode and the respective initialization, the st10f276 scans the rxd0 line to receive a zero byte, that is, 1 start bit, eight ?0? data bits and 1 stop bit. from the duration of this zero byte, it calculates the corresponding baud rate factor with respect to the current cpu clock, initializes the serial interf ace asc0 accordingly and switches pin txd0 to output. using this baud rate, an acknowledge byte is returned to the host that provides the loaded data. the acknowledge byte is d5h for the st10f276. rstin txd0 int. boot rom / test-flash bsl-routine 32 bytes 2) 3) rxd0 csp:ip user software 4) 6) p0l.4 1) bsl initialization time, > 1ms @ fcpu = 40 mhz. 2) zero byte (1 start bit, eight ?0? data bits, 1 stop bit), sent by host. 3) acknowledge byte, sent by st10f276. 4) 32 bytes of code / data, sent by host. 5) caution: txd0 is only driven a certain time after reception of the zero byte (1.3ms @ fcpu = 40 mhz). 6) internal boot rom / test-flash. 1) 5)
st10f276 bootstrap loader 55/229 5.3.3 st10 configuration in uart bsl (rs232 or k-line) when the st10f276 enters bsl mode on uart, the configuration shown in ta bl e 3 0 is automatically set (values that deviate from the normal reset values are marked in bold ). other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. pin txd0 is configured as output, so the st10f276 can return the acknowledge byte. even if the internal iflash is enabled, a code cannot be executed from it. 5.3.4 loading the start-up code after sending the acknowledge byte, the bsl enters a loop to receive 32 bytes via asc0. these bytes are stored sequentially into locations 00?fa40 h through 00?fa5f h of the iram, allowing up to 16 instructions to be placed into the ram area. to execute the loaded code the bsl then jumps to location 00?fa40h, that is, the first loaded instruction. the bootstrap loading sequence is now terminated; however, the st10f276 remains in bsl mode. the initially loaded routine will most probably load additional co de or data, as an average application is likely to require substantially mo re than 16 instructions. this second receive loop may directly use the pre-initialized inte rface asc0 to receive data and store it in arbitrary user-defined locations. this second level of loaded code may be the final application code another, more sophisticated, loader routin e that adds a transmission protocol to enhance the integrity of the loaded code or data a code sequence to change the system configuration and enable the bus interface to store the received data into external memory table 30. st10 configuration in uart bsl mode (rs232 or k-line) function or register access notes watchdog timer disabled register syscon 0400 h (1) 1. in bootstrap modes (standard or alternate) romen, bit 10 of syscon, is always set regardless of ea pin level. bytdis, bit 9 of syscon, is set according to data bus width selection via port0 configuration. context pointer cp fa00 h register stkun fa00 h stack pointer sp fa40 h register stkov fc00 h register buscon0 acc. to startup config. (2) 2. buscon0 is initialized with 0000h, external bus disabled, if pin ea is high during reset. if pin ea is low during reset, busact0, bit 10, and alectl0, bit 9, are set enabling the external bus with lengthened ale signal. btyp field, bit 7 and 6, is set according to port0 configuration. register s0con 8011 h initialized only if bootstrap via uart register s0bg acc. to ?00? byte initialized only if bootstrap via uart p3.10 / txd0 ? 1 ? initialized only if bootstrap via uart dp3.10 ? 1 ? initialized only if bootstrap via uart
bootstrap loader st10f276 56/229 this process may go through several iterations or may directly execute the final application. in all cases the st10f276 still ru ns in bsl mode, that is, with the watchdog timer disabled and limited access to the internal flash area. all code fetches from the internal iflash area (01?0000 h ...08?ffff h ) are redirected to the special test-flash. data read operations access the internal flash of the st10f276. 5.3.5 choosing the baud ra te for the bsl via uart the calculation of the serial baud rate for asc0 from the length of the first zero byte that is received allows the operation of the bootstrap loader of the st10f276 with a wide range of baud rates. however, the upper and lower limits must be kept to ensure proper data transfer. the st10f276 uses timer t6 to measure the length of the initial zero byte. the quantization uncertainty of this measurement implies the first deviation from the real baud rate; the next deviation is implied by the computation of the s0brl reload value from the timer contents. the formula below shows the association: for a correct data transfer from the host to the st10f276, the maximum deviation between the internal initialized baud rate for asc0 and the real baud rate of the host should be below 2.5%. the deviation (f b , in percent) between host baud rate and st10f276 baud rate can be calculated using the formula below: note: function (f b ) does not consider the tolerances of oscillators and othe r devices supporting the serial communication. this baud rate deviation is a nonlinear func tion depending on the cpu clock and the baud rate of the host. the maxima of the function (f b ) increases with the host baud rate due to the smaller baud rate prescaler factors and the implied higher quantization error (see figure 10). figure 10. baud rate deviation between host and st10f276 the minimum baud rate (b low in figure 10) is determined by the maximum count capacity of timer t6, when measuring the zero byte, that is, it depends on the cpu clock. using the maximum t6 count 2 16 in the formula the minimum baud rate is calculated. the lowest f cpu 32 s0brl 1 + () ? ------------------------------------------ - b st10f276 = s0brl t6 36 ? 72 ------------------- - = t6 9 4 -- f cpu b host --------------- ? = , b low 2.5% f b b high i ii b host
st10f276 bootstrap loader 57/229 standard baud rate in this case would be 1200 baud. baud rates below b low would cause t6 to overflow. in this case, asc0 cannot be initialized properly. the maximum baud rate (b high in figure 10 ) is the highest baud rate where the deviation still does not exceed the limit, th at is, all baud rates between b low and b high are below the deviation limit. the maximum stand ard baud rate that fu lfills this requirement is 19200 baud. higher baud rates , however, may be used as long as the actual deviation does not exceed the limit. a certain baud rate (marked ?i? in figure 10 ) may, for example, violate the deviation limit, while an even higher baud rate (marked ?ii? in figure 10 ) stays well below it. this depends on the host interface. 5.4 standard bootstrap with can 5.4.1 features the bootstrap via can has the same overall behavior as the bootstrap via uart: same bootstrapping steps; same bootstrap method: analyze the timing of a predefined frame, send back an acknowledge frame but only on request , load a fixed number of bytes and run; same functionalities: boot with different crystals and pll ratios. figure 11. can bootst rap loader sequence the bootstrap loader can load the complete application software into rom-less systems, temporary software into complete systems for testing or calibration, a programming routine for flash devices. int. boot rom / test-flash bsl-routine 128bytes 2) 3) user software 4) 6) 1) bsl initialization time, > 1ms @ fcpu = 40 mhz. 2) zero frame (can message: standard id = 0, dlc = 0), sent by host. 3) can message (standard id = e6h, dlc = 3, data0 = d5h, data1-data2 = idchip_low-high), sent by st10f276 on request. 4) 128 bytes of code / data, sent by host. 5) caution: can1_txd is only driven a certain time afte r reception of the zero byte (1.3ms @ fcpu = 40 mhz). 6) internal boot rom / test-flash . 1) 5) p0l.4 can1_txd can1_rxd csp:ip rstin
bootstrap loader st10f276 58/229 the bsl mechanism may be used for standard system start-up as well as for only special occasions like system maintenance (firmware update) or end-of- line programming or testing. 5.4.2 entering the can bootstrap loader the st10f276 enters bsl mode if pin p0l.4 is sampled low at the end of a hardware reset. in this case, the built-in bootstrap loader is activated independently of the selected bus mode. the bootstrap loader code is stored in a special test-flash; no part of the standard mask rom or flash memory area is required for this. after entering bsl mode and the respective initialization, the st10f276 scans the can1_txd line to receive the following initialization frame: ? standard identifier = 0h ? dlc = 0h as all the bits to be transmitted are dominant bits, a succession of 5 dominant bits and 1 stuff bit on the can network is used. from the duration of this frame, it calculates the corresponding baud rate factor with respect to the current cpu clock, initializes the can1 interface accordingly, switches pin can1_txd to output and enables the can1 interface to take part in the network communication. using this baud rate, a message object is configured in order to send an acknowledge frame. the st 10f276 will not send this message object but the host can request it by sending a remote frame. the acknowledge frame is the following for the st10f276: ? standard identifier = e6h ? dlc = 3h ? data0 = d5h, that is, generic acknowledge of the st10 devices ? data1 = idchip least significant byte ? data2 = idchip most significant byte for the st10f276, idchip = 114xh. note: two behaviors can be distinguished in st10 acknowledging to the host. if the host is behaving according to the can protocol, as at the beginning the st10 can is not configured, the host is alone on the can network and does not receive an acknowledge. it automatically resends the zero frame. as soon as the st10 can is configured, it acknowledges the zero frame. the ?acknowledge frame? with identifier 0xe6 is configured, but the transmit request is not set. the host can request this frame to be sent and therefore obtains the idchip by sending a remote frame. hint: as the idchip is sent in the acknowledge frame, flash programming software now can immediately identify the exact type of device to be programmed.
st10f276 bootstrap loader 59/229 5.4.3 st10 configur ation in can bsl when the st10f276 enters bsl mode via can, the configuration shown in ta bl e 3 1 is automatically set (values that deviate from the normal reset values are marked in bold ). other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. pin can1_txd1 is configured as output, so the st10f276 can return the identification frame. even if the internal iflash is enabled, a code cannot be executed from it. 5.4.4 loading the start-up code via can after sending the acknowledge byte, the bsl enters a loop to receive 128 bytes via can1. hint: the number of bytes loaded when booting via the can interface has been extended to 128 bytes to allow the reconfiguration of the can bit timing register with the best timings (synchronization window, ...). this can be achieved by the following sequence of instructions: reconfigurebaud rate: mov r1,#041h mov dpp3:0ef00h,r1 ; put can in init, enable configuration change mov r1,#01600h mov dpp3:0ef06h,r1 ; 1mbaud at fcpu = 20 mhz these 128 bytes are stored sequentially into locations 00?fa40 h through 00?fabf h of the iram, allowing up to 64 instructions to be placed into the ram area. to execute the loaded code the bsl then jumps to location 00?fa40 h , that is, the first loaded instruction. the bootstrap loading sequence is now terminated; however, the st10f276 remains in bsl table 31. st10 configuration in can bsl function or register access notes watchdog timer disabled register syscon 0404 h (1) 1. in bootstrap modes (standard or alternate) romen, bit 10 of syscon, is always set regardless of ea pin level. bytdis, bit 9 of syscon, is set according to data bus width selection via port0 configuration. xpen bit set context pointer cp fa00 h register stkun fa00 h stack pointer sp fa40 h register stkov fc00 h register buscon0 acc. to startup config. (2) 2. buscon0 is initialized with 0000h, external bus disabled, if pin ea is high during reset. if pin ea is low during reset, busact0, bit 10, and alectl0, bit 9, are set enabling the external bus with lengthened ale signal. btyp field, bit 7 and 6, is set according to port0 configuration. can1 status/control register 0000 h initialized only if bootstrap via can can1 bit timing register acc. to ?0? fr ame initialized only if bootstrap via can xpercon 042d h xram1-2, xflash, can1 and xmisc enabled p4.6 / can1_txd ?1? initialized only if bootstrap via can dp4.6 ?1? initialized only if bootstrap via can
bootstrap loader st10f276 60/229 mode. most probably the init ially loaded routine will load additional code or data, as an average application is likely to require substant ially more than 64 instructions. this second receive loop may directly use t he pre-initialized can interface to receive data and store it in arbitrary user-defined locations. this second level of loaded code may be the final application code another, more sophisticated, loader routin e that adds a transmission protocol to enhance the integrity of the loaded code or data a code sequence to change the system configuration and enable the bus interface to store the received data into external memory this process may go through several iterations or may directly execute the final application. in all cases the st10f276 still ru ns in bsl mode, that is, with the watchdog timer disabled and limited access to the internal flash area. all code fetches from the internal flash area (01?0000 h ...08?ffff h ) are redirected to th e special test-flash. data read operations will access the internal flash of the st10f276. 5.4.5 choosing the baud ra te for the bsl via can the bootstrap via can acts the same way as in the uart bootstrap mode. when the st10f276 is started in bsl mode, it polls the rxd0 and can1_rxd lines. when polling a low level on one of these lines, a timer is launched that is stopped when the line returns to high level. for can communication, the algorithm is made to receive a zero frame, that is, the standard identifier is 0x0, dlc is 0. this frame produc es the following levels on the network: 5d, 1r, 5d, 1r, 5d, 1r, 5d, 1r, 5d, 1r, 4d, 1r, 1d, 11r. the algorithm lets the timer run until the detection of the 5 th recessive bit. this way the bit timing is calculated over the duration of 29 bit times: this minimizes the error introduced by the polling . figure 12. bit rate measurement over a predefined zero-frame ........ start stuff bit stuff bit stuff bit stuff bit measured time
st10f276 bootstrap loader 61/229 error induced by the polling the code used for the polling is the following: waitcom: jnb p4.5,can_boot ; if sof detected on can, then go to can ; loader jb p3.11,waitcom ; wait for start bit at rxd0 bset t6r ; start timer t6 .... can_boot: bset pwmcon0.0 ; start pwm timer0 ; (resolution is 1 cpu clk cycle) jmpr cc_uc,waitrecessivebit waitdominantbit: jb p4.5,waitdominantbit; wait for end of stuff bit waitrecessivebit: jnb p4.5,waitrecessivebit; wait for 1st dominant bit = stuff bit cmpi1r1,#5 ; test if 5th stuff bit detected jmpr cc_ne,waitdominantbit; no, go back to count more bclr pwmcon.0 ; stop timer ; here the 5th stuff bit is detected: ; pt0 = 29 bit_time (25d and 4r) therefore the maximum error at the detection of the communication on can pin is: (1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 cpu clock cycles the error at the detection for the 5 th recessive bit is: (1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 cpu cycles in the worst case, the induced error is 6 cpu clock cycles, so the po lling could induce an error of 6 timer ticks. error induced by the baud rate calculation the content of the timer pt0 counter corresponds to 29 bit times, resulting in the following equation: pt0 = 58 x (brp + 1) x (1 + tseg1 + tseg2) where brp, tseg1 and tseg2 are the fi eld of the can bit timing register. the can protocol specification recommends to implement a bit time composed of at least 8 time quanta (tq). this recommendation is applied here. moreover, the maximum bit time length is 25 tq. to ensure precision, the aim is to have the smallest bit rate prescaler (brp) and the maximum number of tq in a bit time. this gives the following ranges for pt0 according to brp: 8 1 + tseg1 + tseg2 25 464 x (1 + brp) pt0 1450 x (1 + brp)
bootstrap loader st10f276 62/229 the error coming from the measurement of the 29 bit is: e 1 = 6 / [pt0] it is maximal for the smallest brp value and the smallest number of ticks in pt0. therefore: e 1 max = 1.29% to improve precision, the aim is to have the smallest brp so that the time quantum is the smallest possible. thus, an error on the calculation of time quanta in a bit time is minimal. in order to do so, the value of pt0 is divided into ranges of 1450 ticks. in the algorithm, pt0 is divided by 1451 and the result is brp. the calculated brp value is then used to divide pt0 in order to have the value of (1 + tseg1 + tseg2) . a table is made to set the values for tseg1 and tseg2 according to the value of (1 + tseg1 + tseg2) . these values of tseg1 and tseg2 are chosen in order to reach a sample point between 70% and 80% of the bit time. during the calculation of (1 + tseg1 + tseg2) , an error e 2 can be introduced by the division. this error is of 1 time quantum maximum. to compensate for any possible error on bit rate, the (re)synchronization jump width is fixed to 2 time quanta. table 32. brp and pt0 values brp pt0_min pt0_max comments 0 464 1450 1 1451 2900 2 2901 4350 3 4351 5800 4 5801 7250 5 7251 8700 .. .. .. 43 20416 63800 44 20880 65250 45 21344 66700 possible timer overflow .. .. .. 63 x x
st10f276 bootstrap loader 63/229 5.4.6 computing the baud rate error considering the following conditions, a computation of the error is given as an example. cpu frequency: 20 mhz target bit rate: 1 mbit/s in these conditions, the content of pt0 timer for 29 bits should be: therefore: 574 < [pt0] < 586 this gives: brp = 0 tq = 100 ns computation of 1 + tseg1 + tseg2 : considering the equation: [pt0] = 58 x (1 + brp) x (1 + tseg1 + tseg2) thus: in the algorithm, a rounding up to the superior value is made if the remainder of the division is greater than half of the divisor. this would have been the case if the pt0 content was 574. thus, in this example the result is 1 + tseg1 + tseg2 = 10 , giving a bit time of exactly 1 s => no error in bit rate. note: in most cases (24 mhz, 32 mhz, 40 mhz of cpu frequency and 125, 250, 500 or 1mb/s of bit rate), there is no error. nevertheless, it is better to check for an error with the real application parameters. the content of the bit timing register is: 0x1640 . this gives a sample point at 80%. note: the (re)synchronization jump width is fixed to 2 time quanta. 5.4.7 bootstrap via can after the bootstrap phase, the st10f276 can module is configured as follows: the pin p4.6 is configured as output (the latch value is ?1? = recessive) to assume can1_txd function. the mo2 is configured to output the acknowledge of the bootstrap with the standard identifier e6h, a dlc of 3 and data0 = d5h, data1 and 2 = idchip. the mo1 is configured to receive messages with the standard identifier 5h. its acceptance mask is set to ensure that all bits match. the dlc received is not checked: the st10 expects only 1 byte of data at a time. no other message is sent by the st10f276 after the acknowledge. note: the can boot waits for 128 bytes of data instead of 32 bytes (see uart boot). this is done to allow the user to reconfigure the can bit rate as soon as possible. pt0 [] 29 fcpu bitrate -------------------------- - 29 20 6 110 6 ---------------------------- - 580 = = = 9 574 58 --------- - tseg1 tseg2 586 58 --------- -10 = + =
bootstrap loader st10f276 64/229 5.5 comparing the old and the new bootstrap loader the following tables summarizes the differences between the old st10 (boot via uart only) bootstrap and the new one (boot via uart or can). 5.5.1 software aspects as the can1 is needed, xpercon register is configured by the bootstrap loader code and bit xpen of syscon is set. however, as long as the einit instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. to do this, perform the following steps: disable the xperipherals by clearing xpen in syscon regist er. attention: if this part of the code is located in xram, it will be disabled. enable the needed xperipherals by writ ing the correct value in xpercon register. set xpen bit in syscon. table 33. software topics summary old bootstrap loader new bootstrap loader comments uses only 32 bytes in dual- port ram from 00?fa40h uses up to 128 bytes in dual-port ram from 00?fa40h for compatibility between boot via uart and boot via can1, please avoid loading the application software in the 00?fa60h/00?fabfh range. loads 32 bytes from uart loads 32 bytes from uart (boot via uart mode) same files can be used for boot via uart. user selected xperipherals can be enabled during boot (step 3 or step 4). xperipherals selection is fixed. user can change the xperipherals selections through a specific code.
st10f276 bootstrap loader 65/229 5.5.2 hardware aspects although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements for the new bootstrap loader as summarized in ta b l e 3 4 . 5.6 alternate bo ot mode (abm) 5.6.1 activation alternate boot is activated with the combination ?01? on port0l[5..4] at the rising edge of rstin . 5.6.2 memory mapping the st10f276 has the same memory mapping for standard boot mode and for alternate boot mode: test-flash: mapped from 00?0000h. the standard bootstrap loader can be started by executing a jump to the address of this routine (jmps 00?xxxx; address to be defined ). user flash: the user flash is divided in two parts: the iflash, visible only for memory reads and memory writes (no code fetch) and the xflash, visible for any st10 access (memory read, memory write and code fetch). all st10f276 xram and xperipherals modules can be accessed if enabled in xpercon register. note: the alternate boot mode can be used to reprogram the whole content of the st10f276 user flash (except block 0 in bank 2, w here the alternate boot is mapped into). 5.6.3 interrupts the st10 interrupt vector table is always mapped from address 00?0000h. as a consequence, interrupts are not allowed in alternate boot mode; all maskable and nonmaskable interrupts must be disabled. table 34. hardware topics summary actual bootstrap loader ne w bootstrap loader comments p4.5 can be used as output in bsl mode. p4.5 cannot be used as user output in bsl mode, but only as can1_rxd or input or address segments. level on can1_rxd can change during boot step 2. level on can1_rxd must be stable at ?1? during boot step 2. external pull-up on p4.5 needed.
bootstrap loader st10f276 66/229 5.6.4 st10 configuration in alternate boot mode when the st10f276 enters bsl mode via can, the configuration shown in ta bl e 3 5 is automatically set (values that deviate from the normal reset values are marked in bold ). even if the internal iflash is enabled, a code cannot be executed from it. as the xflash is needed, xperco n register is configured by the abm loader code and bit xpen of syscon is set. however, as long as the einit instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified. to do this, perform the following steps: copy in dpram a function that will ? disable the xperipherals by clearing xpen in syscon register, ? enabled the needed xperi pherals by writing the correct value in xpercon register, ? set xpen bit in syscon, ? return to calling address. call the function from xflash the changing of the xpercon value cannot be executed from the xflash because the xflash is disabled by the clearing of xpen bit in syscon. 5.6.5 watchdog as for standard boot, the watchdog timer remains disabled during alternate boot mode. in case a watchdog reset occurs, a software reset is generated. note: see note from section 5.2.7 concerning software reset. 5.6.6 exiting alternate boot mode once the abm mode is entered, it can be exited only with a software or hardware reset. note: see note from section 5.2.7 concerning software reset. table 35. st10 configuration in alternate boot mode function or register access notes watchdog timer disabled register syscon 0404h (1) 1. in bootstrap modes (standard or alternate) romen, bit 10 of syscon, is always set regardless of ea pin level. bytdis, bit 9 of syscon, is set according to data bus width selection via port0 configuration. xpen bit set context pointer cp fa00 h register stkun fa00 h stack pointer sp fa40 h register stkov fc00 h register buscon0 acc. to startup config. (2) 2. buscon0 is initialized with 0000h, external bus disabled, if pin ea is high during reset. if pin ea is low during reset, busact0, bit 10, and alectl0, bit 9, are set enabling the external bus with lengthened ale signal. btyp field, bit 7 and 6, is set according to port0 configuration. xpercon 002d h xram1-2, xflash, can1 enabled
st10f276 bootstrap loader 67/229 5.6.7 alternate boot user software if the rules described previously are respected (that is, mapping of variables, disabling of interrupts, exit conditions, predefined vectors in block 0 of bank 2, watchdog usage), then users can write the software they want to execute in this mode starting from 09?0000h. 5.6.8 user/alternate mode signature integrity check the behavior of the alternate boot mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature. this requires that users who use alternate boot have reserved and programmed the flash memory locations according to: user mode signature 00'0000h: memory address of operand0 for the signature computing 00?1ffch: memory address of operand1 for the signature computing 00?1ffeh: memory address for the signature reference alternate mode signature 09'0000h: memory address of operand0 for the signature computing 09?1ffch: memory address of operand1 for the signature computing 09?1ffeh: memory address for the signature reference the values for operand0, operand1 and the signature should be such that the sequence shown in the figure below is successfully executed. mov rx, checkblock1addr; 00?0000h for standard reset add rx, checkblock2addr; 00?1ffch for standard reset cplb rlx ; 1s complement of the lower ; byte of the sum cmp rx, checkblock3addr; 00?1ffeh for standard reset 5.6.9 alternate boot user software aspects user defined alternate boot code must start at 09?0000h. a new sfr created on the st10f276 indicates that the device is running in alternate boot mode: bit 5 of emucon (mapped at 0xfe0ah) is set when the alternate boot is selected by the reset configuration. all the other bits are ignored when checking the content of this register to read the value of bit 5. this bit is a read-only bit. it remains set until the next software or hardware reset. 5.6.10 emucon register emucon (fe0ah / 05h) sfr reset value: - xxh: 1514131211109876543210 - abm -r-
bootstrap loader st10f276 68/229 5.6.11 internal d ecoding of test modes the test mode decoding logic is located inside the st10f276 bus controller. the decoding is as follows: alternate boot mode decoding: (p0l.5 & p0l.4) standard bootstrap decoding: (p0l.5 & p0l.4 ) normal operation: (p0l.5 & p0l.4) the other configurations select st internal test modes. 5.6.12 example in the following example, alternate boot mode works as follows: ? on rising edge of rstin pin, the reset configuration is latched. if bootstrap loader mode is not enabled (p0l[5..4] = ?11?), st10f276 hardware proceeds with a standard hardware reset procedure. if standard bootstrap loader is enabled (p0l[5..4] = ?10?), the standard st10 bootstrap loader is enabled and a variable is cleared to indicate that abm is not enabled. if alternate boot mode is selected (p0l[5..4] = ?01?), then, depending on signatures integrity checks, a predefined reset sequence is activated. 5.7 selective boot mode the selective boot is a subcase of the alternate boot mode. when none of the signatures are correct, instead of executing the standard bootstrap loader (triggered by p0l.4 low at reset), an additional check is made. address 00?1ffch is read again with the following behavior: if value is 0000h or ffffh, a jump is performed to the standard bootstrap loader. otherwise: ? high byte is disregarded. ? low byte bits select which communication channel is enabled. table 36. abm bit description bit function abm abm flag (or tmod3) ?0?: alternate boot mode is not select ed by reset configuration on p0l[5..4] ?1?: alternate boot mode is selected by rese t configuration on p0l[ 5..4]: this bit is set if p0l[5..4] = ?01? during hardware reset.
st10f276 bootstrap loader 69/229 therefore a value: 0xxx03 configures the selective bootstrap loader to poll for rxd0 and can1_rxd. 0xxx01 configures the selective bootstrap loader to poll only rxd0 (no boot via can). 0xxx02 configures the selective bootstrap loader to poll only can1_rxd (no boot via uart). other values allow the st10f276 to execute an endless loop into the test-flash. table 37. selective boot bit function 0 uart selection ?0?: uart is not watched for a start condition. ?1?: uart is watched for a start condition. 1 can1 selection ?0?: can1 is not watched for a start condition. ?1?: can1 is watched for a start condition. 2..7 reserved for upward compatibility, must be programmed to ?0?
bootstrap loader st10f276 70/229 figure 13. reset boot sequence standard start k2 is not ok no (p0l[5..4] = ?11?) k2 is ok k1 is not ok k1 is ok running from test flash yes (p0l[5..4] = ?01?) abm / user flash start at 09?0000h std. bootstrap loader jump to test-flash user mode / user flash start at 00?0000h rstin 0 to 1 boot mode? yes (p0l[5..4] = ?10?) software checks user reset vector (k1 is ok?) software checks alternate reset vector (k2 is ok?) long jump to 09?0000h sw reset st test modes no (p0l[5..4] = ?other config.?) selective boot strap loader jump to test-flash read 00?1ffch
st10f276 central processing unit (cpu) 71/229 6 central processing unit (cpu) the cpu includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedicated sfrs. additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. most of the st10f276?s instructions can be executed in one instruction cycle which requires 31.25ns at 64 mhz cpu clock. for example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles. the jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. the cpu uses a bank of 16 word registers to run the current context. this bank of general purpose registers (gpr) is physically stored within the on-chip internal ram (iram) area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 2048 bytes is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. figure 14. cpu block diagram (mac unit not included) 32 internal ram 2kbyte general purpose registers r0 r15 mdh mdl barrel-shift mul./div.-hw bit-mask gen. alu 16-bit cp sp stkov stkun exec. unit instr. ptr 4-stage pipeline psw syscon buscon 0 buscon 1 buscon 2 buscon 3 buscon 4 addrsel 1 addrsel 2 addrsel 3 addrsel 4 data pg. ptrs code seg. ptr. cpu 512 kbyte flash memory 16 16 bank n bank i bank 0
central processing unit (cpu) st10f276 72/229 6.1 multiplier-accumulator unit (mac) the mac coprocessor is a specialized coprocessor added to the st10 cpu core in order to improve the performances of the st10 family in signal processing algorithms. the standard st 10 cpu has been modified to include new addressing capabilities which enable the cpu to supply the new coprocessor with up to 2 operands per instruction cycle. this new coprocessor (so-called mac) contains a fast multiply-accumulate unit and a repeat unit. the coprocessor instructions extend the st10 cpu instruction set with multiply, multiply- accumulate, 32-bit signed arithmetic operations. figure 15. mac unit architecture operand 2 operand 1 control unit repeat unit st10 cpu interrupt controller msw mrw mah mal mcw flags mae mux 8-bit left/right shifter mux mux sign extend 16 x 16 concatenation signed/unsigned multiplier 40-bit signed arithmetic unit 0h 0h 08000h 40 16 40 40 32 32 16 40 40 40 40 40 scaler ab 40 gpr pointers * idx0 pointer idx1 pointer qr0 gpr offset register qr1 gpr offset register qx0 idx offset register qx1 idx offset register
st10f276 central processing unit (cpu) 73/229 6.2 instruction set summary the ta bl e 3 8 lists the instructions of the st10f276. the detailed description of each instruction can be found in the ?st10 family programming manual?. table 38. standard instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement dire ct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bit-wise and, (word/byte operands) 2 / 4 or(b) bit-wise or, (word/byte operands) 2 / 4 xor(b) bit-wise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bit-wise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indir ect/relative if condition is met 4 jmps jump absolute to a code segment 4
central processing unit (cpu) st10f276 74/229 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative s ubroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 38. standard instruction set summary (continued) mnemonic description bytes
st10f276 central processing unit (cpu) 75/229 6.3 mac coprocessor specific instructions the ta bl e 3 9 lists the mac instructions of the st10f276. the detailed description of each instruction can be found in the ?st10 family programming manual?. note that all mac instructions are encoded on 4 bytes. table 39. mac instruction set summary mnemonic description coabs absolute value of the accumulator coadd(2) addition coashr(rnd) accumulator arithmetic shift right & optional round cocmp compare accumulator with operands coload(-,2) load accumulator with operands comac(r,u,s,-,rnd) (un)signed/(un)signed multiply-accumulate & optional round comacm(r)(u,s,-,rnd) (un)signed/(un)signed multiply-accumulate with parallel data move & optional round comax / comin maximum / minimum of operands and accumulator comov memory to memory move comul(u,s,-,rnd) (un)signed/(un)signed multiply & optional round coneg(rnd) negate accumulator & optional round conop no-operation cornd round accumulator coshl / coshr accumulator logical shift left / right costore store a mac unit register cosub(2,r) substraction
external bus controller st10f276 76/229 7 external bus controller all of the external memory accesses are performed by the on-chip external bus controller. the ebc can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed in demultiplexed bus modes addresses are output on port1 and data is input / output on port0 or p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input / output. timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. up to four independent address windows may be defined (using register pairs addrselx / busconx) to access different res ources and bus characteristics. these address windows are arranged hierar chically where buscon4 overrides buscon3 and buscon2 overrides buscon1. all accesses to locations not covered by these four address windows are controlled by buscon0. up to five external cs signals (four windows plus default) can be generated in order to save external glue logic. access to very slow memories is supported by a ?ready? function. a hold / hlda protocol is available for bus arbitration which shares external resources with other bus masters. the bus arbitration is enabled by setting bit hlden in register psw. after setting hlden once, pins p6.7...p6.5 (breq , hlda , hold ) are automatically controlled by the ebc. in master mode (default after reset) the hlda pin is an output. by setting bit dp6.7 to?1? the slave mode is selected where pin hlda is switched to input. this directly connects the slave controller to another master controller without glue logic. for applications which require less external memory space, the address space can be restricted to 1 mbyte, 256 kbytes or to 64 kbytes. port 4 outputs all eight address lines if an address space of 16m bytes is used, otherwise four, two or no address lines. chip select timing can be made programmable. by default (after reset), the csx lines change half a cpu clock cycle after the rising edge of ale. with the cscfg bit set in the syscon register the csx lines change with the rising edge of ale. the active level of the ready pin can be set by bit rdypol in the busconx registers. when the ready function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit rdypol in the associated buscon register.
st10f276 interrupt system 77/229 8 interrupt system the interrupt response time for internal program execution is from 78ns to 187.5ns at 64 mhz cpu clock. the st10f276 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. any of these interrupt requests can be serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source or destination pointer. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited to perform the transmission or the reception of blocks of data. the st10f276 has 8 pec channels, each of them offers such fast interrupt-driven da ta transfer capabilities. an interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. once starting to be processed by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). fast external interrupts may also have interrupt sources selected from other peripherals; for example the canx controller receive signals (canx_rxd) and i 2 c serial clock signal can be used to interrupt the system. table 40 shows all the available st10f276 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: table 40. interrupt sources source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number capcom register 0 cc0ir cc0ie cc0int 00?0040h 10h capcom register 1 cc1ir cc1ie cc1int 00?0044h 11h capcom register 2 cc2ir cc2ie cc2int 00?0048h 12h capcom register 3 cc3ir cc3ie cc3int 00?004ch 13h capcom register 4 cc4ir cc4ie cc4int 00?0050h 14h capcom register 5 cc5ir cc5ie cc5int 00?0054h 15h
interrupt system st10f276 78/229 capcom register 6 cc6ir cc6ie cc6int 00?0058h 16h capcom register 7 cc7ir cc7ie cc7int 00?005ch 17h capcom register 8 cc8ir cc8ie cc8int 00?0060h 18h capcom register 9 cc9ir cc9ie cc9int 00?0064h 19h capcom register 10 cc10ir cc10ie cc10int 00?0068h 1ah capcom register 11 cc11ir cc11ie cc11int 00?006ch 1bh capcom register 12 cc12ir cc12ie cc12int 00?0070h 1ch capcom register 13 cc13ir cc13ie cc13int 00?0074h 1dh capcom register 14 cc14ir cc14ie cc14int 00?0078h 1eh capcom register 15 cc15ir cc15ie cc15int 00?007ch 1fh capcom register 16 cc16ir cc16ie cc16int 00?00c0h 30h capcom register 17 cc17ir cc17ie cc17int 00?00c4h 31h capcom register 18 cc18ir cc18ie cc18int 00?00c8h 32h capcom register 19 cc19ir cc19ie cc19int 00?00cch 33h capcom register 20 cc20ir cc20ie cc20int 00?00d0h 34h capcom register 21 cc21ir cc21ie cc21int 00?00d4h 35h capcom register 22 cc22ir cc22ie cc22int 00?00d8h 36h capcom register 23 cc23ir cc23ie cc23int 00?00dch 37h capcom register 24 cc24ir cc24ie cc24int 00?00e0h 38h capcom register 25 cc25ir cc25ie cc25int 00?00e4h 39h capcom register 26 cc26ir cc26ie cc26int 00?00e8h 3ah capcom register 27 cc27ir cc27ie cc27int 00?00ech 3bh capcom register 28 cc28ir cc28ie cc28int 00?00f0h 3ch capcom register 29 cc29ir cc29ie cc29int 00?0110h 44h capcom register 30 cc30ir cc30ie cc30int 00?0114h 45h capcom register 31 cc31ir cc31ie cc31int 00?0118h 46h capcom timer 0 t0ir t0ie t0int 00?0080h 20h capcom timer 1 t1ir t1ie t1int 00?0084h 21h capcom timer 7 t7ir t7ie t7int 00?00f4h 3dh capcom timer 8 t8ir t8ie t8int 00?00f8h 3eh gpt1 timer 2 t2ir t2ie t2int 00?0088h 22h gpt1 timer 3 t3ir t3ie t3int 00?008ch 23h gpt1 timer 4 t4ir t4ie t4int 00?0090h 24h gpt2 timer 5 t5ir t5ie t5int 00?0094h 25h table 40. interrupt sources (continued) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number
st10f276 interrupt system 79/229 hardware traps are exceptions or error conditions that arise during run-time. they cause immediate non-maskable system reaction simila r to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. hardwa re trap services cannot not be interrupted by standard interrupt or by pec interrupts. 8.1 x-peripheral interrupt the limited number of x-bus interrupt lines of the present st10 architecture, imposes some constraints on the implementation of the new functionality. in particular, the additional x- peripherals ssc1, asc1, i 2 c, pwm1 and rtc need some resources to implement interrupt and pec transfer capabilities. for this reas on, a multiplexed structure for the interrupt management is proposed. in the next figure 16 , the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four x-interrupt available vectors (xp0int, xp1int, xp2int and xp3int). it is based on a set of 16-bit registers xirxse l (x=0,1,2,3), divided in two portions each: byte high xirxsel[15:8] interrupt enable bits byte low xirxsel[7:0] interrupt flag bits when different sources submit an interrupt request, the enable bits (byte high of xirxsel register) define a mask which controls which sources will be associated with the unique gpt2 timer 6 t6ir t6ie t6int 00?0098h 26h gpt2 caprel register crir crie crint 00?009ch 27h a/d conversion complete adcir adcie adcint 00?00a0h 28h a/d overrun error adeir adeie adeint 00?00a4h 29h asc0 transmit s0tir s0tie s0tint 00?00a8h 2ah asc0 transmit buffer s0tbir s0tbie s0tbint 00?011ch 47h asc0 receive s0rir s0rie s0rint 00?00ach 2bh asc0 error s0eir s0eie s0eint 00?00b0h 2ch ssc transmit sctir sctie sctint 00?00b4h 2dh ssc receive scrir scrie scrint 00?00b8h 2eh ssc error sceir sceie sceint 00?00bch 2fh pwm channel 0...3 pwmir pwmie pwmint 00?00fch 3fh see paragraph 8.1 xp0ir xp0ie xp0int 00?0100h 40h see paragraph 8.1 xp1ir xp1ie xp1int 00?0104h 41h see paragraph 8.1 xp2ir xp2ie xp2int 00?0108h 42h see paragraph 8.1 xp3ir xp3ie xp3int 00?010ch 43h table 40. interrupt sources (continued) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number
interrupt system st10f276 80/229 available vector. if more than one source is enabled to issue the request, the service routine will have to take care to identify the real even t to be serviced. this can easily be done by checking the flag bits (byte low of xirxsel register). note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt reques t: a periodic polling of the flag bits may be implemented inside the user application. figure 16. x-interrupt basic structure the ta bl e 4 1 summarizes the mapping of the different interrupt sources which shares the four x-interrupt vectors. table 41. x-interrupt detailed mapping xp0int xp1int xp2int xp3int can1 interrupt xx can2 interrupt xx i2c receive xxx i2c transmit xxx i2c error x ssc1 receive xxx ssc1 transmit xxx ssc1 error x asc1 receive xxx asc1 transmit xxx asc1 transmit buffer xxx xir x sel[7:0] (x = 0, 1, 2, 3) xir x sel[15:8] (x = 0, 1, 2, 3) xp x ic . xp x ir (x = 0, 1, 2, 3) 7 0 15 8 it source 7 it source 6 it source 5 it source 4 it source 3 it source 2 it source 1 it source 0 enable[7:0] flag[7:0]
st10f276 interrupt system 81/229 8.2 exception and error traps list ta bl e 4 2 shows all of the possible exceptions or error conditions that can arise during run- time. note: * - all the class b traps have the same trap number (and vector) and the same lower priority compare to the class a traps and to the resets. - each class a traps has a dedicated trap number (and vector). they are prioritized in the second priority level. - the resets have the highest priority level and the same trap number. - the psw.ilvl cpu priority is forced to the highest level (15) when these exceptions are serviced. asc1 error x pll unlock / owd x pwm1 channel 3...0 xx table 41. x-interrupt detailed mapping (continued) xp0int xp1int xp2int xp3int table 42. trap priorities exception condition trap flag trap vector vector location trap number trap* priority reset functions: hardware reset software reset watchdog timer overflow reset reset reset 00?0000h 00?0000h 00?0000h 00h 00h 00h iii iii iii class a hardware traps: non-maskable interrupt stack overflow stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00?0008h 00?0010h 00?0018h 02h 04h 06h ii ii ii class b hardware traps: undefined opcode mac interruption protected instruction fault illegal word operand access illegal instruction access illegal external bus access undopc mactrp prtflt illopa illina illbus btrap btrap btrap btrap btrap btrap 00?0028h 00?0028h 00?0028h 00?0028h 00?0028h 00?0028h 0ah 0ah 0ah 0ah 0ah 0ah i i i i i i reserved [002ch - 003ch] [0bh - 0fh] software traps trap instruction any 0000h ? 01fch in steps of 4h any [00h - 7fh] current cpu priority
capture / compare (capcom) units st10f276 82/229 9 capture / compare (capcom) units the st10f276 has two 16-channel capcom units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125ns at 64 mhz cpu clock. the capcom units are typically used to handl e high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, software timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. in addition, external count inputs for capcom timers t0 and t7 allow event scheduling for the capture/compare registers relative to external events. each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, respectively), and programmed for capture or compare functions. each of the 32 registers has one associated port pin which serv es as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positi ve and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture / compare register, specific actions will be take n based on the selected compare mode. the input frequencies f tx , for the timer input selector tx, are determined as a function of the cpu clocks. the timer input frequencies, resolution and periods which result from the selected pre-scaler option in txi when using a 40 mhz and 64 mhz cpu clock are listed in the ta b l e 4 4 and ta b l e 4 5 respectively. the numbers for the timer periods are based on a reload value of 0000h. note that some numbers may be rounded to 3 significant figures.
st10f276 capture / compare (capcom) units 83/229 table 43. compare modes compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; severa l compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on match; pin reset ?0? on compare time overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. table 44. capcom timer input frequencies, resolutions and periods at 40 mhz f cpu = 40 mhz timer input selection txi 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler for f cpu 8 16 32 64 128 256 512 1024 input frequency 5mhz 2.5mhz 1.25mhz 625 khz 312.5 khz 156.25 khz 78.125 khz 39.1 khz resolution 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s 25.6s period 13.1ms 26.2ms 52.4ms 104.8 ms 209.7ms 419.4ms 838.9ms 1.678s table 45. capcom timer input frequencies, resolutions and periods at 64 mhz f cpu = 64 mhz timer input selection txi 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler for f cpu 8 16 32 64 128 256 512 1024 input frequency 8mhz 4mhz 2mhz 1 khz 500 khz 250 khz 128 khz 64 khz resolution 125ns 250ns 0.5s 1.0s 2.0s 4.0s 8.0s 16.0s period 8.2ms 16.4ms 32.8ms 65.5m s 131.1ms 262.1ms 524.3ms 1.049s
general purpose timer unit st10f276 84/229 10 general purpose timer unit the gpt unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gp t unit contains five 16-bit timers organized into two separate modules gpt1 and gpt2. each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 10.1 gpt1 each of the three timers t2, t3, t4 of the gpt1 module can be configured individually for one of four basic modes of operation: timer , gated timer , counter mode and incremental interface mode . in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler. in counter mode, the timer is clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the ?gate? level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. table 46 and table 47 list the timer input frequencies, resolution and periods for each pre- scaler option at 40mhz and 64mhz cpu clock respectively. in incremental interface mode, the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b by their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals so that the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has output toggle latches (txotl) which changes state on each timer over flow / underflow. the state of this latch may be output on port pins (txout) for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for high resolution of long duration measurements. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. table 46. gpt1 timer input frequencies, resolutions and periods at 40 mhz f cpu = 40 mhz timer input selection t2i / t3i / t4i 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler factor 8 16 32 64 128 256 512 1024 input frequency 5mhz 2.5mhz 1.25 mhz 625 khz 312.5 khz 156.25 khz 78.125 khz 39.1 khz
st10f276 general purpose timer unit 85/229 figure 17. block diagram of gpt1 resolution 200ns 400ns 0.8s 1 .6s 3.2s 6.4s 12.8s 25.6s period maximum 13.1ms 26.2ms 52.4ms 104.8 ms 209.7ms 419.4ms 838.9ms 1.678s table 47. gpt1 timer input frequencies, resolutions and periods at 64 mhz f cpu = 64 mhz timer input selection t2i / t3i / t4i 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler factor 8 16 32 64 128 256 512 1024 input freq 8mhz 4mhz 2mhz 1 khz 500 khz 250 khz 128 khz 64 khz resolution 125ns 250ns 0.5s 1.0s 2.0s 4.0s 8.0s 16.0s period maximum 8.2ms 16.4ms 32.8ms 65.5ms 131 .1ms 262.1ms 524.3ms 1.049s table 46. gpt1 timer input frequencies, resolutions and periods at 40 mhz f cpu = 40 mhz timer input selection t2i / t3i / t4i 000b 001b 010b 011b 100b 101b 110b 111b 2n n=3...10 2n n=3...10 2n n=3...10 t2eud t2in cpu clock cpu clock cpu clock t3in t4in t3eud t4eud gpt1 timer t2 gpt1 timer t3 gpt1 timer t4 t3otl reload capture u/d u/d reload capture interrupt request interrupt request interrupt request t3out u/d t2 mode control t3 mode control t4 mode control
general purpose timer unit st10f276 86/229 10.2 gpt2 the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported via the output toggle latch (t6otl) of timer t6 which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, or it may be output on a port pin (t6out). the overflow / underflow of timer t6 can additionally be used to clock the capcom timers t0 or t1, and to cause a re load from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture procedure. this allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. the capture trigger (timer t5 to caprel) may also be generated upon transitions of gpt1 timer t3 inputs t3in and/or t3eud. this is advantageous when t3 operates in incremental interface mode. ta bl e 4 8 and ta bl e 4 9 list the timer input frequencies, resolution and periods for each pre- scaler option at 40mhz and 64mhz cpu clock respectively. table 48. gpt2 timer input frequencies, resolutions and periods at 40 mhz f cpu = 40mhz timer input selection t5i / t6i 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler factor 4 8 16 32 64 128 256 512 input freq 10mhz 5mhz 2.5mhz 1.25 mhz 625 khz 312.5 khz 156.25 khz 78.125 khz resolution 100ns 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104 .8ms 209.7ms 419.4ms 838.9ms table 49. gpt2 timer input frequencies, resolutions and periods at 64 mhz f cpu = 64mhz timer input selection t5i / t6i 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler factor 4 8 16 32 64 128 256 512 input freq 16mhz 8mhz 4mhz 2mhz 1 khz 500 khz 250 khz 128 khz resolution 62.5ns 125ns 250ns 0.5s 1.0s 2.0s 4.0s 8.0s period maximum 4.1ms 8.2ms 16.4ms 32.8ms 65. 5ms 131.1ms 262.1ms 524.3ms
st10f276 general purpose timer unit 87/229 figure 18. block diagram of gpt2 2n n=2...9 2n n=2...9 t5eud t5in cpu clock cpu clock t6in t6eud gpt2 timer t5 gpt2 timer t6 u/d interrupt request u/d gpt2 caprel t60tl toggle ff t6out capin reload interrupt request to capcom timers capture clear interrupt request t5 mode control t6 mode control
pwm modules st10f276 88/229 11 pwm modules two pulse width modulation modules are available on st10f276: standard pwm0 and xbus pwm1. they can generate up to four pwm output signals each, using edge-aligned or centre-aligned pwm. in addition, the pwm modules can generate pwm burst signals and single shot outputs. the ta bl e 5 0 and ta b l e 5 1 show the pwm frequencies for different resolutions. the level of the output signals is selectable and the pwm modules can generate interrupt requests. figure 19. block diagram of pwm module table 50. pwm unit frequencies and resolutions at 40 mhz cpu clock mode 0 resolution 8-bit 10- bit 12-bit 14-bit 16-bit cpu clock/1 25ns 156.25 khz 39.1 khz 9.77 khz 2.44hz 610hz cpu clock/64 1.6 s 2.44 khz 610hz 152.6hz 38.15hz 9.54hz mode 1 resolution 8-bit 10- bit 12-bit 14-bit 16-bit cpu clock/1 25ns 78.12 khz 19.53 khz 4.88 khz 1.22 khz 305.2hz cpu clock/64 1.6 s 1.22 khz 305.17hz 76.29hz 19.07hz 4.77hz table 51. pwm unit frequencies and resolutions at 64 mhz cpu clock mode 0 resolution 8-bit 10- bit 12-bit 14-bit 16-bit cpu clock/1 15.6ns 250 khz 62.5 khz 15.63 khz 3.91hz 977hz cpu clock/64 1.0 s 3.91 khz 976.6hz 244.1hz 61.01hz 15.26hz mode 1 resolution 8-bit 10- bit 12-bit 14-bit 16-bit cpu clock/1 15.6ns 125 khz 31.25 khz 7.81 khz 1.95 khz 488.3hz cpu clock/64 1.0 s 1.95 khz 488.28hz 122.07hz 30.52hz 7.63hz ppx period register comparator ptx 16-bit up/down counter shadow register pwx pulse width register input run control clock 1 clock 2 comparator * * * up/down/ clear control match output control match write control * user readable / writeable register enable poutx
st10f276 parallel ports 89/229 12 parallel ports 12.1 introduction the st10f276 mcu provides up to 111 i/o lines with programmable features. these capabilities bring very flexible adaptation of this mcu to wide range of applications. st10f276 has nine groups of i/o lines gathered as follows: port 0 is a two time 8-bit port named p0l (low as less significant byte) and p0h (high as most significant byte) port 1 is a two time 8-bit port named p1l and p1h port 2 is a 16-bit port port 3 is a 15-bit port (p3.14 line is not implemented) port 4 is a 8-bit port port 5 is a 16-bit port input only port 6, port 7 and port 8 are 8-bit ports these ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. for example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bit- wise) for push-pull or open drain operation using odpx registers. the input threshold levels are programmable (ttl/cmos) for all the ports. the logic level of a pin is clocked into the input latch once pe r state time, regardless whether the port is configured for input or output. the threshold is selected with picon and xpicon registers control bits. a write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. a read- modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. writing to a pin configured as an output (dpx.y=?1?) causes the output latch and the pin to have the written value, since the output buffer is enabled. reading this pin returns the value of the output latch. a read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. i/o lines support an alternate function which is detailed in the following description of each port.
parallel ports st10f276 90/229 12.2 i/o?s special features 12.2.1 open drain mode some of the i/o ports of st10 f276 support the open drain capability. this programmable feature may be used with an external pull-up resistor, in order to get an and wired logical function. this feature is implemented for ports p2, p3, p4, p6, p7 and p8 (see respective sections), and is controlled through the respective open drain control registers odpx. 12.2.2 input thre shold control the standard inputs of the st10f276 determine the status of input signals according to ttl levels. in order to accept and recognize noi sy signals, cmos input thresholds can be selected instead of the standard ttl thresholds for all the pins. these cmos thresholds are defined above the ttl thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. the port input control registers picon and xpicon are used to select these thresholds for each byte of the indicated ports, this means the 8-bit ports p0l, p0h, p1l, p1h, p4, p7 and p8 are controlled by one bit each while ports p2, p3 and p5 are controlled by two bits each. all options for individual direction and output mode control are available for each pin, independent of the selected input threshold. 12.3 alternate port functions each port line has one associated programmable alternate input or output function. port0 and port1 may be used as address and data lines when accessing external memory. besides, port1 provides also: ? input capture lines ? 8 additional analog input channels to the a/d converter port 2, port 7 and port 8 are associated with the capture inputs or compare outputs of the capcom units and/or with the outputs of the pwm0 module, of the pwm1 module and of the asc1. port 2 is also used for fast external interrupt inputs and for timer 7 input. port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal bhe and the system clock output (clkout). port 4 outputs the additional segment address bit a23...a16 in systems where more than 64 kbytes of memory are to be access directly. in addition, can1, can2 and i 2 c lines are provided. port 5 is used as analog input channels of the a/d converter or as timer control signals. port 6 provides optional bus arbitration signals (breq , hlda , hold ) and chip select signals and the ssc1 lines. if the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (dpx.y=?1?), except for some signals that are used directly after reset and are configured automatically. otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. the respective port latch should hold a
st10f276 parallel ports 91/229 ?1?, because its output is anded with the alternate output data (except for pwm output signals). if the alternate input function of a pin is used, the direction of the pin must be programmed for input (dpx.y=?0?) if an external device is dr iving the pin. the input direction is the default after reset. if no external device is connecte d to the pin, however, one can also set the direction for this pin to output. in this case, the pin reflects the state of the port output latch. thus, the alternate input function reads the value stored in the port output latch. this can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. on most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. this is done by setting or clearing the direction control bit dpx.y of the pin before enabling the alternate function. there are port lines, however, where the direction of the port line is switched automatically. for instance, in the multiplexed external bus modes of port0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. obviously, this cannot be done through instructions. in these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. to determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output. there is one basic structure for all port lines with only an alternate input function. port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. all port lines that are not used for these alte rnate functions may be used as general purpose i/o lines.
a/d converter st10f276 92/229 13 a/d converter a 10-bit a/d converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. an automatic self-calibration adjusts the a/d converter module to process parameter variations at each reset event. the sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. the st10f273e has 16+8 multiplexed input channels on port 5 and port 1. the selection between port 5 and port 1 is made via a bit in a xbus register. refer to the user manual for a detailed description. a different accuracy is guaranteed (total unadjusted error) on port 5 and port 1 analog channels (with higher restrictions when overload conditions occur); in particular, port 5 channels are more accurate than the port 1 one s. refer to electrical characteristic section for details. the a/d converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5lsb (2mv) impacting the global tue (tue depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 khz. of course, to reduce the effect of the input signal variation on the accuracy down to 0.05lsb, the maximum input frequency of the sine wave shall be reduced to 800 hz. if static signal is applied during sampling phase, series resistance shall not be greater than 20k ? (this taking into account eventual input leakage). it is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an rc filter is necessary the external capacitance must be greater than 10nf to minimize the accuracy impact. overrun error detection / protection is controlled by the addat register. either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. for applications which require less than 16+8 analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converter of the st10f276 supports different conversion modes: single channel single conversion : the analog level of the selected channel is sampled once and converted. the result of the conversion is stored in the addat register. single channel continuous conversion : the analog level of the selected channel is repeatedly sampled and converted. the result of the conversion is stored in the addat register. auto scan single conversion : the analog level of the selected channels are sampled once and converted. after each conversion the result is stored in the addat register. the data can be transferred to the ram by interrupt software management or using the powerful peripheral event controller (pec) data transfer. auto scan continuous conversion : the analog level of the selected channels are repeatedly sampled and converted. the result of the conversion is stored in the addat
st10f276 a/d converter 93/229 register. the data can be transferred to the ram by interrupt software management or using the pec data transfer. wait for addat read mode : when using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the adwr bit of adcon control register must be activated. then, until the addat register is read, the new result is stored in a temporary buffer and the conversion is on hold. channel injection mode : when using continuous modes, a selected channel can be converted in between without changing the current operating mode. the 10-bit data of the conversion are stored in adres field of addat2. the current continuous mode remains active after the single conversion is completed. a full calibration sequence is performed after a reset. this full calibration lasts up to 40.630 cpu clock cycles. during this time, the busy flag adbsy is set to indica te the operation. it compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. no conversion can be performed during this time: the bit adbsy shall be polled to verify when the calibration is over, and the module is able to start a convertion.
serial channels st10f276 94/229 14 serial channels serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (asc0 and asc1) and two high-speed synchronous serial channel (ssc0 and ssc1). dedicated baud rate generators set up all standard baud rates without the requirement of oscillator tuning. for transm ission, reception and erroneous reception, separate interrupt vectors are provided for asc0 and ssc0 serial channel. a more complex mechanism of interrupt sources multiplexing is implemented for asc1 and ssc1 (xbus mapped). 14.1 asynchronous / sync hronous serial interfaces the asynchronous / synchronous serial interfaces (asc0 and asc1) provides serial communication between the st10f276 and other microcontrollers, microprocessors or external peripherals. 14.2 ascx in asynchronous mode in asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. parity framing and overrun error detection is provided to increase the reliability of data transfers. transmission and reception of data is double-buffered. full- duplex communication up to 2m bauds (at 64 mhz of f cpu ) is supported in this mode. table 52. asc asynchronous baud rates by reload value and deviation errors (f cpu = 40 mhz) s0brs = ?0?, f cpu = 40 mhz s0brs = ?1?, f cpu = 40 mhz baud rate (baud) deviation error reload value (hex) baud rate (baud) deviation error reload value (hex) 1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -7.0% 000a / 000b 112 000 +6.3% / -7.0% 0006 / 0007 56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000d / 000e 38 400 +1.7% / -1.4% 001f / 0020 38 400 +3.3% / -1.4% 0014 / 0015 19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002a / 002b 9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056 4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00ac / 00ad 2 400 +0.2% / 0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015a / 015b 1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02b5 / 02b6 600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056b / 056c 300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0ad8 / 0ad9 153 0.0% / 0.0% 1fe8 / 1fe9 102 0.0% / 0.0% 1fe8 / 1fe9
st10f276 serial channels 95/229 note: the deviation errors given in the ta bl e 5 2 and ta b l e 5 3 are rounded. to avoid deviation errors use a baud rate crystal (providing a multiple of the asc0 sampling frequency). 14.3 ascx in synchronous mode in synchronous mode, data is transmitted or rece ived synchronously to a shift clock which is generated by the st10f276. half-duplex communication up to 8m baud (at 40 mhz of f cpu ) is possible in this mode. table 53. asc asynchronous baud rates by reload value and deviation errors (f cpu = 64 mhz) s0brs = ?0?, f cpu = 64 mhz s0brs = ?1?, f cpu = 64 mhz baud rate (baud) deviation error reload value (hex) baud rate (baud) deviation error reload value (hex) 2 000 000 0.0% / 0.0% 0000 / 0000 1 333 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -7.0% 0010 / 0011 112 000 +6.3% / -7.0% 000a / 000b 56 000 +1.5% / -3.0% 0022 / 0023 56 000 +6.3% / -0.8% 0016 / 0017 38 400 +1.7% / -1.4% 0033 / 0034 38 400 +3.3% / -1.4% 0021 / 0022 19 200 +0.2% / -1.4% 0067 / 0068 19 200 +0.9% / -1.4% 0044 / 0045 9 600 +0.2% / -0.6% 00cf / 00d0 9 600 +0.9% / -0.2% 0089 / 008a 4 800 +0.2% / -0.2% 019f / 01a0 4 800 +0.4% / -0.2% 0114 / 0115 2 400 +0.2% / 0.0% 0340 / 0341 2 400 +0.1% / -0.2% 022a / 015b 1 200 0.1% / 0.0% 0681 / 0682 1 200 +0.1% / -0.1% 0456 / 0457 600 0.0% / 0.0% 0d04 / 0d05 600 +0.1% / 0.0% 08ad / 08ae 300 0.0% / 0.0% 1a09 / 1a0a 300 0.0% / 0.0% 115b / 115c 245 0.0% / 0.0% 1fe2 / 1fe3 163 0.0% / 0.0% 1ff2 / 1ff3 table 54. asc synchronous baud rates by reload value and deviation errors (f cpu = 40 mhz) s0brs = ?0?, f cpu = 40 mhz s0brs = ?1?, f cpu = 40 mhz baud rate (baud) deviation error reload value (hex) baud rate (baud) deviation error reload value (hex) 5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -0.8% 002b / 002c 112 000 +2.6% / -0.8% 001c / 001d 56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003a / 003b 38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056 19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00ac / 00ad 9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015a / 015b 4 800 +0.1% / 0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02b5 / 02b6 2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / 0.0% 056b / 056c 1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0ad8 / 0ad9
serial channels st10f276 96/229 note: the deviation errors given in the ta bl e 5 4 and ta b l e 5 5 are rounded. to avoid deviation errors use a baud rate crystal (providing a multiple of the asc0 sampling frequency) 14.4 high speed synchronous serial interfaces the high-speed synchronous serial interfaces (ssc0 and ssc1) provides flexible high- speed serial communication between the st10f276 and other microcontrollers, microprocessors or external peripherals. the sscx supports full-duplex and half-duplex synchronous communication. the serial clock signal can be generated by the sscx itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data is double-buffered. a 16-bit baud rate generator provides the sscx with a separate serial clock signal. the serial channel sscx has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. 900 0.0% / 0.0% 15b2 / 15b3 600 0.0% / 0.0% 15b2 / 15b3 612 0.0% / 0.0% 1fe8 / 1fe9 407 0.0% / 0.0% 1ffd / 1ffe table 54. asc synchronous baud rates by reload value and deviation errors (f cpu = 40 mhz) s0brs = ?0?, f cpu = 40 mhz s0brs = ?1?, f cpu = 40 mhz baud rate (baud) deviation error reload value (hex) baud rate (baud) deviation error reload value (hex) table 55. asc synchronous baud rates by reload value and deviation errors (f cpu = 64 mhz) s0brs = ?0?, f cpu = 64 mhz s0brs = ?1?, f cpu = 64 mhz baud rate (baud) deviation error reload value (hex) baud rate (baud) deviation error reload value (hex) 8 000 000 0.0% / 0.0% 0000 / 0000 5 333 333 0.0% / 0.0% 0000 / 0000 112 000 +0.6% / -0.8% 0046 / 0047 112 000 +1.3% / -0.8% 002e / 002f 56 000 +0.6% / -0.1% 008d / 008e 56 000 +0.3% / -0.8% 005e / 005f 38 400 +0.2% / -0.3% 00cf / 00d0 38 400 +0.6% / -0.1% 0089 / 008a 19 200 +0.2% / -0.1% 019f / 01a0 19 200 +0.3% / -0.1% 0114 / 0115 9 600 +0.0% / -0.1% 0340 / 0341 9 600 +0.1% / -0.1% 022a / 022b 4 800 0.0% / 0.0% 0681 / 0682 4 800 0.0% / -0.1% 0456 / 0457 2 400 0.0% / 0.0% 0d04 / 0d05 2 400 0.0% / 0.0% 08ad / 08ae 1 200 0.0% / 0.0% 1a09 / 1a0a 1 200 0.0% / 0.0% 115b / 115c 977 0.0% / 0.0% 1ffb / 1ffc 900 0.0% / 0.0% 1724 / 1725 652 0.0% / 0.0% 1ff2 / 1ff3
st10f276 serial channels 97/229 ta bl e 5 6 and ta b l e 5 7 list some possible baud rates against the required reload values and the resulting bit times for 40 mhz and 64 mhz cpu clock respectively. the maximum is anyway limited to 8mbaud. table 56. synchronous baud rate and reload values (f cpu = 40 mhz) baud rate bit time reload value reserved --- 0000h can be used only with f cpu = 32 mhz (or lower) --- 0001h 6.6m baud 150ns 0002h 5m baud 200ns 0003h 2.5m baud 400ns 0007h 1m baud 1 s 0013h 100k baud 10 s 00c7h 10k baud 100 s07cfh 1k baud 1ms 4e1fh 306 baud 3.26ms ff4eh table 57. synchronous baud rate and reload values (f cpu = 64 mhz) baud rate bit time reload value reserved --- 0000h can be used only with f cpu = 32 mhz (or lower) --- 0001h can be used only with f cpu = 48 mhz (or lower) --- 0002h 8m baud 125ns 0003h 4m baud 250ns 0007h 1m baud 1 s 001fh 100k baud 10 s 013fh 10k baud 100 s0c7fh 1k baud 1ms 7cffh 489 baud 2.04ms ff9eh
i2c interface st10f276 98/229 15 i2c interface the integrated i 2 c bus module handles the transmission and reception of frames over the two-line sda/scl in accordance with the i 2 c bus specification. the i 2 c module can operate in slave mode, in master mode or in multi-master mode. it can receive and transmit data using 7-bit or 10-bit addressing. data can be transferred at speeds up to 400 kbit/s (both standard and fast i 2 c bus modes are supported). the module can generate three different types of interrupt: requests related to bus events, like start or stop events, arbitration lost, etc. requests related to data transmission requests related to data reception these requests are issued to the interrupt cont roller by three different lines, and identified as error, transmit, and re ceive interrupt lines. when the i 2 c module is enabled by setting bit xi2cen in xpercon register, pins p4.4 and p4.7 (where scl and sda are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. p4, dp4 and odp4 cannot influence the pin configuration. when the i 2 c cell is disabled (clearing bit xi2cen), p4.4 and p4.7 pins are standard i/ o controlled by p4, dp4 and odp4. the speed of the i 2 c interface may be selected between standard mode (0 to 100 khz) and fast i 2 c mode (100 to 400 khz).
st10f276 can modules 99/229 16 can modules the two integrated can modules (can1 and can2) are identical and handle the completely autonomous transmission and reception of can frames according to the can specification v2.0 part b (active). it is based on the c-can specification. each on-chip can module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. because of duplication of the can controllers, the following adjustments are to be considered: same internal register addresses of both can controllers, but with base addresses differing in address bit a8; separate chip select for each can module. refer to chapter 4: internal flash memory . the can1 transmit line (can1_txd) is the alternate function of the port p4.6 pin and the receive line (can1_rxd) is the alternate function of the port p4.5 pin. the can2 transmit line (can2_txd) is the alternate function of the port p4.7 pin and the receive line (can2_rxd) is the alternate function of the port p4.4 pin. interrupt request lines of the can1 and can2 modules are connected to the xbus interrupt lines together with other x-peripherals sharing the four vectors. the can modules must be selected with corresponding canxen bit of xpercon register before the bit xpen of syscon register is set. the reset default configuration is: can1 enabled, can2 disabled. note: if one or both can modules is used, port 4 cannot be programmed to output all 8 segment address lines. thus, only four segment address lines can be used, reducing the external memory space to 5 mbytes (1 mbyte per cs line). 16.1 configuration support it is possible that both can controllers are working on the same can bus, supporting together up to 64 message objects. in this configuration, both receive signals and both transmit signals are linked together when using the same can transceiver. this configuration is especially supported by providing open drain outputs for the can1_txd and can2_txd signals. the open drain function is controlled with the odp4 register for port p4: in this way it is possible to connect together p4.4 with p4.5 (receive lines) and p4.6 with p4.7 (transmit lines configured to be configured as open-drain). the user is also allowed to map internally both can modules on the same pins p4.5 and p4.6. in this way, p4.4 and p4.7 may be used either as general purpose i/o lines, or used for i 2 c interface. this is possible by setting bit canpar of xmisc register. to access this register it is necessary to set bit xmisce n of xpercon register and bit xpen of syscon register.
can modules st10f276 100/229 16.2 can bus configurations depending on application, can bus configuration may be one single bus with a single or multiple interfaces or a multip le bus with a single or multip le interfaces. the st10f276 is able to support these two cases. single can bus the single can bus multiple interfaces configuration may be implemented using two can transceivers as shown in figure 20 . figure 20. connection to single can bus via separate can transceivers the st10f276 also supports single can bus multiple (dual) interfaces using the open drain option of the canx_txd output as shown in figure 21 . thanks to the or-wired connection, only one transceiver is required. in this case the design of the application must take in account the wire length and the noise environment. figure 21. connection to single can bus via common can transceivers can1 rx tx can_h can_l can bus can2 rx tx xmisc.canpar = 0 can can transceiver transceiver p4.4 p4.7 p4.5 p4.6 od = open drain output +5v can can_h can_l can bus 2.7kw od transceiver xmisc.canpar = 0 can1 rx tx can2 rx tx p4.4 p4.7 p4.5 p4.6 od
st10f276 can modules 101/229 multiple can bus the st10f276 provides two can interfaces to support such kind of bus configuration as shown in figure 22 . figure 22. connect ion to two different can buses (e.g. for gateway application) parallel mode in addition to previous configurations, a parallel mode is supported. this is shown in figure 23 . figure 23. connection to one can bus with internal parallel mode enabled can_h can_l can bus 1 can_h can_l can bus 2 xmisc.canpar = 0 can1 rx tx can2 rx tx can can transceiver transceiver p4.4 p4.7 p4.5 p4.6 xmisc.canpar = 1 can2 rx tx p4.4 p4.7 p4.5 p4.6 can can_h can_l can bus transceiver can1 rx tx (both can enabled) 1. p4.4 and p4.7 when not used as can fu nctions can be used as general purpose i/o while they cannot be used as external bus address lines.
real time clock st10f276 102/229 17 real time clock the real time clock is an independent timer, in which the clock is derived directly from the clock oscillator on xtal1 (main oscillator) inpu t or xtal3 input (32 khz low-power oscillator) so that it can be kept on running even in idle or power down mode (if enabled to). registers access is implemented onto the xbus. this module is designed with the following characteristics: generation of the current time and date for the system cyclic time based interrupt, on port2 externa l interrupts every ?rtc basic clock tick? and after n ?rtc basic clock ticks? ( n is programmable) if enabled 58-bit timer for long term measurement capability to exit the st10 chip from power down mode (if pwdcfg of syscon set) after a programmed delay the real time clock is based on two main blocks of counters. the first block is a prescaler which generates a basic reference clock (for example a 1 second period). this basic reference clock is coming out of a 20-bit divider. this 20-bit counter is driven by an input clock derived from the on-chip cpu clock, pre-divided by a 1/64 fixed counter. this 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit prescaler register. the value of the 20-bit rtcp register determines the period of the basic reference clock. a timed interrupt request (rtcsi) may be sent on each basic reference clock period. the second block of the rtc is a 32-bit counter that may be initialized with the current system time. this counter is driven with the basic reference clock signal. in order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. the alarm register may be loaded with a reference date. an alarm interrupt request (rtcai), may be generated when the value of the counter matches the alarm register. the timed rtcsi and the alarm rtcai interrupt requests can trigger a fast external interrupt via exisel register of port 2 and wake-up the st10 chip when running power down mode. using the rtcoff bit of rtccon register, the user may switch off the clock oscillator when entering the power down mode. the last function implem ented in the rtc is to switch off the main on-chip oscillator and the 32 khz on chip oscillato r if the st10 enters the power do wn mode, so that the chip can be fully switched off (if rtc is disabled). at power on, and after reset phase, if the pr esence of a 32 khz oscillation on xtal3 / xtal4 pins is detected, then the rtc counter is driven by this low frequency reference clock: when power down mode is entered, the rtc can either be stopped or left running, and in both the cases the main oscillator is turned off, re ducing the power consumption of the device to the minimum required to keep on running the rtc counter and relative reference oscillator. this is valid also if st and-by mode is entered (switching off the main supply v dd ), since both the rtc and the low power oscillator (3 2 khz) are biased by the v stby . vice versa, when at power on and after reset, the 32 khz is not present, the main oscillator drives the rtc counter, and since it is powered by the main power supply, it cannot be maintained running in stand-by mode, while in power down mode the main oscillator is maintained running to provide the reference to th e rtc module (if not disabled).
st10f276 watchdog timer 103/229 18 watchdog timer the watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. the watchdog timer is always enabled after a reset of the chip and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. therefore, the chip start-up procedure is always monitored. the software must be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. it pulls the rstout pin low in order to allow external hardware components to be reset. each of the different reset sources is indicated in the wdtcon register: watchdog timer reset in case of an overflow software reset in case of execution of the srst instruction short, long and power-on reset in case of hardware reset (and depending of reset pulse duration and rpd pin configuration) the indicated bits are cleared with the einit instruction. the source of the reset can be identified during the initialization phase. the watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. the high byte of the watchdog timer register can be set to a pre-specified reload value (stored in wdtrel). each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. for security, rewrite wdtcon each time before the watchdog timer is serviced the ta bl e 5 8 and ta bl e 5 9 show the watchdog time range for 40 mhz and 64 mhz cpu clock respectively. table 58. wdtrel reload value (f cpu = 40 mhz) reload value in wdtrel prescaler for f cpu = 40 mhz 2 (wdtin = ?0?) 128 (wdtin = ?1?) ffh 12.8 s 819.2 s 00h 3.277ms 209.7ms table 59. wdtrel reload value (f cpu = 64 mhz) reload value in wdtrel prescaler for f cpu = 64 mhz 2 (wdtin = ?0?) 128 (wdtin = ?1?) ffh 8 s 512 s 00h 2.048ms 131.1ms
system reset st10f276 104/229 19 system reset system reset initializes the mcu in a predefined state. there are six ways to activate a reset state. the system start-up configuration is different for each case as shown in ta b l e 6 0 . 1) rstin pulse should be longer than 500ns (filter) and than settling time for configuration of port0. 2) see next section 19.1 for more details on minimum reset pulse duration. 3) the rpd status has no influence unless bidirectional reset is activated (bit bdrsten in syscon): rpd low inhibits the bidirectional reset on sw and wdt reset events, that is rstin is not activated (refer to sections 19.4 , 19.5 and 19.6 ). 19.1 input filter on rstin input pin an on-chip rc filter is implemented. it is sized to filter all the spikes shorter than 50ns. on the other side, a valid pulse shall be longer than 500ns to grant that st10 recognizes a reset command. in between 50ns and 500ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations. for this reason all minimum durations mentioned in this chapter for the different kind of reset events shall be carefully evaluated taking into account of the above requirements. in particular, for short hardware reset, wher e only 4 tcl is specified as minimum input reset pulse duration, the operating frequency is a key factor. examples: for a cpu clock of 64 mhz, 4 tcl is 31.25ns, so it would be filtered. in this case the minimum becomes the one imposed by the filter (that is 500ns). for a cpu clock of 4 mhz, 4 tcl is 500ns. in this case the minimum from the formula is coherent with the limi t imposed by the filter. table 60. reset event definition reset source flag rpd status conditions power-on reset ponr low power-on asynchronous hardware reset lhwr low t rstin > 1) synchronous long hardware reset high t rstin > (1032 + 12) tcl + max(4 tcl, 500ns) synchronous short hardware reset shwr high t rstin > max(4 tcl, 500ns) t rstin (1032 + 12) tcl + max(4 tcl, 500ns) watchdog timer reset wdtr 3) wdt overflow software reset swr 3) srst instruction execution
st10f276 system reset 105/229 19.2 asynchronous reset an asynchronous reset is triggered when rstin pin is pulled low while rpd pin is at low level. then the st10f276 is immediately (after the input filter delay) forced in reset default state. it pulls low rstout pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and i/o pin drivers to high-impedance, it pulls high port0 pins. note: if an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended. power-on reset the asynchronous reset must be used during the power-on of the device. depending on crystal or resonator frequency, the on-c hip oscillator needs ab out 1ms to 10ms to stabilize (refer to electrical characterist ics section), with an already stable v dd . the logic of the st10f276 does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. to ensure a proper reset sequence, the rstin pin and the rpd pin must be held at low level unt il the device clock signal is stabilized and the system configuration value on port0 is settled. at power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules. in particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8v for the core logic: this time is computed from when the external reference (v dd ) becomes stable (inside specification range, that is at least 4.5v). this is a constraint for the application hardware (external voltage regulator): the rstin pin assertion shall be extended to guarantee the volta ge regulator stabilization. a second constraint is imposed by the embedded flash. when booting from internal memory, starting from rstin releasing, it needs a maximum of 1ms for its initialization: before that, the internal reset (rst signal) is not released, so the cpu does not start code execution in internal memory. note: this is not true if external memory is used (pin ea held low during reset phase). in this case, once rstin pin is released, and after few cpu clock (filter delay plus 3...8 tcl), the internal reset signal rst is released as well, so the code execution can start immediately after. obviously, an eventual access to the data in internal flash is forbidden before its initialization phase is complete d: an eventual access during starting phase will return ffffh (just at the beginning), wh ile later 009bh (an illegal opc ode trap can be generated). at power-on, the rstin pin shall be tied low for a minimum time that includes also the start- up time of the main oscillator (t stup = 1ms for resonator, 10ms for crystal) and pll synchronization time (t psup = 200 s): this means that if the internal flash is used, the rstin pin could be released before the main oscillator and pll are stable to recover some time in the start-up phase (flash initialization only needs stable v 18 , but does not need stable system clock since an inte rnal dedicated oscillator is used). warning: it is recommended to provide the external hardware with a current limitation circuitry. this is necessary to avoid permanent damages of the device during the power-on transient, when the capacitance on v 18 pin is charged. for the on-chip voltage regulator functionality 10nf are
system reset st10f276 106/229 sufficient: anyway, a maximum of 100nf on v 18 pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware). external current limitation is anyway recommended also to avoid risks of damage in case of temporary short between v 18 and ground: the internal 1.8v drivers are sized to drive currents of several tens of ampere, so the current shall be limited by the external hardware. the limit of current is imposed by power dissipation considerations (refer to electrical characteristics section). in next figures 24 and 25 asynchronous power-on timing diagrams are reported, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded flash module when selected. note: never power the device without keeping rstin pin grounded: the device could enter in unpredictable states, risking also permanent damages.
st10f276 system reset 107/229 figure 24. asynchronous power-on reset (ea = 1) rstf p0[15:13] p0[12:2] transparent transparent p0[1:0] not t. not transparent flarst v 18 xtal1 ... 2 tcl rst 1 ms latching point of port0 for system start-up configuration v dd 1 ms (for on-chip vreg stabilization) rpd ibus-cs 1.2 ms (for resonator oscillation + pll stabilization) 10.2 ms (for crystal oscillation + pll stabilization) rstin (after filter) 500 ns 50 ns 7 tcl 3..4 tcl (internal) not t. not t. not t.
system reset st10f276 108/229 figure 25. asynchronous power-on reset (ea = 0) hardware reset the asynchronous reset must be used to recover from catastrophic situations of the application. it may be triggered by the hardware of the application. internal hardware logic and application circuitry are described in reset circuitry chapter and figures 37 , 38 and 39 . it occurs when rstin is low and rpd is detected (or becomes) low as well. rstin p0[15:13] p0[12:2] not t. transparent not t. p0[1:0] not t. not transparent v 18 xtal1 ... 3..8 tcl 1) rst latching point of port0 for system start-up configuration v dd 1 ms (for on-chip vreg stabilization) rpd ale 1.2 ms (for resonator oscillation + pll stabilization) 10.2 ms (for crystal oscillation + pll stabilization) note 1. 3 to 8 tcl depending on clock source selection. rstf 500 ns (after filter) 50 ns 8 tcl transparent 3..4 tcl
st10f276 system reset 109/229 figure 26. asynchronous hardware reset (ea = 1) rstf p0[15:13] p0[12:2] transparent transparent not t. p0[1:0] not t. not transparent flarst 2 tcl rst 1 ms latching point of port0 for system start-up configuration rpd ibus-cs 1) not transparent not transparent note 1. longer than port0 settling time + pll syn chronization (if needed, that is p0(15:13) changed) longer than 500ns to take into acco unt of input filter on rstin pin (after filter) rstin 500 ns 50 ns 500 ns 50 ns 7 tcl (internal) 3..4 tcl not t. not t.
system reset st10f276 110/229 figure 27. asynchronous hardware reset (ea = 0) exit from asynchronous reset state when the rstin pin is pulled high, the device restarts: as already mentioned, if internal flash is used, the restarting occurs after the embedded flash initialization routine is completed. the system configuration is latched from port0: ale, rd and wr /wrl pins are driven to their inactive level. the st10f276 starts program execution from memory location 00'0000h in code segment 0. this starting location will ty pically point to the general initialization routine. timing of asynchronous hardware reset sequence are summarized in figure 26 and figure 27 . 19.3 synchronous reset (warm reset) a synchronous reset is triggered when rstin pin is pulled low while rpd pin is at high level. in order to properly activate the internal reset logic of the device, the rstin pin must be held low, at least, during 4 tcl (2 periods of cpu clock): refer also to section 19.1 for details on minimum reset pulse duration. the i/o pins are set to high impedance and rstout pin is driven low. after rstin level is detected, a short duration of a maximum of 12 tcl (six periods of cpu clock) elapses, du ring which pending internal hold states are cancelled and the current internal access cycle if any is completed. external bus cycle is aborted. the internal pull-down of rstin pin is activated if bit bdrsten of syscon register was previously set by software. note that this bit is always cleared on power-on or after a reset sequence. rstf p0[15:13] p0[12:2] transparent not t. transparent not t. p0[1:0] not t. not transparent 3..8 tcl 2) rst latching point of port0 for system start-up configuration rpd ale 1) note 2. 3 to 8 tcl depending on clock source selection. not transparent not transparent note 1. longer than port0 settling time + pll sync hronization (if needed, that is p0(15:13) changed) longer than 500ns to take into account of input filter on rstin pin (after filter) rstin 500 ns 50 ns 500 ns 50 ns 8 tcl 3..4 tcl
st10f276 system reset 111/229 short and long synchronous reset once the first maximum 16 tcl are elapsed (4+12tcl), the internal reset sequence starts. it is 1024 tcl cycles long: at the end of it, and after other 8tcl the level of rstin is sampled (after the filter, see rstf in the drawings): if it is al ready at high level, only short reset is flagged (refer to chapter 19: system reset for details on rese t flags); if it is recognized still low, the long reset is flagged as well. the major diff erence between long and short reset is that during the long reset, also p0(15:13) become transparent, so it is possible to change the clock options. warning: in case of a short pulse on rstin pin, and when bidirectional reset is enabled, the rstin pin is held low by the internal circuitry. at the end of the 1024 tcl cycles, the rtsin pin is released, but due to the presence of the input analog filter the internal input reset signal (rstf in the drawings) is released later (from 50 to 500ns). this delay is in parallel with the additional 8 tcl, at the end of which the internal input reset line (rstf ) is sampled, to decide if the reset event is short or long. in particular: if 8 tcl > 500ns (f cpu < 8 mhz), the reset event is always recognized as short if 8 tcl < 500ns (f cpu > 8 mhz), the reset event could be recognized either as short or long, depending on the real filter delay (between 50 and 500ns) and the cpu frequency (rstf sampled high means short reset, rstf sampled low means long reset). note that in case a long reset is recognized, once the 8 tcl are elapsed, the p0(15:13) pins becomes transparent, so the system clock can be re-configured. the port returns not transparent 3-4tcl after the internal rstf signal becomes high. the same behavior just described, occurs also when unidirectional reset is selected and rstin pin is held low till the end of the intern al sequence (exactly 1024tcl + max 16 tcl) and released exactly at that time. note: when running with cpu frequency lower than 40 mhz, the minimum valid reset pulse to be recognized by the cpu (4 tcl) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a cpu reset (shorter than 4 tcl): this would generate a flash reset but not a system reset. in this condition, the flash answers always with ffffh, which leads to an illegal op code and consequently a trap event is generated. exit from synchronous reset state the reset sequence is extended until rstin level becomes high. besi des, it is internally prolonged by the flash initialization when ea =1 (internal memory selected). then, the code execution restarts. the system configuration is latched from port0, and ale, rd and wr /wrl pins are driven to their inactive level. the st10f276 starts program execution from memory location 00'0000h in code segment 0. this star ting location will typically point to the general initialization routine. timing of synchronous reset sequence are summarized in figures 28 and 29 where a short reset event is shown, with particular highlighting on the fact that it can degenerate into long reset: the two figures show the behavior when booting from internal or external memory respectively. figures 30 and 31 reports the timing of a typical synchronous long reset, again when booting from internal or external memory.
system reset st10f276 112/229 synchronous reset and rpd pin whenever the rstin pin is pulled low (by external hardware or as a consequence of a bidirectional reset), the rpd internal weak pull-down is activated. the external capacitance (if any) on rpd pin is slowly discharged through the internal weak pull-down. if the voltage level on rpd pin reaches the input low threshold (around 2.5v), the reset event becomes immediately asynchronous. in case of hardware reset (short or long) the situation goes immediately to the one illustrated in figure 26 . there is no effect if rpd comes again above the input threshold: the asynchronous reset is completed coherently. to grant the normal completion of a synchronous reset, the value of the capacitance shall be big enough to maintain the voltage on rpd pin sufficient high along the duration of the internal reset sequence. for a software or watchdog reset events, an active synchronous reset is completed regardless of the rpd status. it is important to highlight that the signal that makes rpd status transparent under reset is the internal rstf (after the noise filter).
st10f276 system reset 113/229 figure 28. synchronous short / long hardware reset (ea = 1) p0[15:13] not transparent rstf p0[12:2] transparent not t. p0[1:0] not t. not transparent flarst rst 1 ms 1024 tcl 2 tcl 2) v rpd > 2.5v asynchronous reset not entered 200 a discharge rpd rstout at this time rstf is sampled high or low so it is short or long reset (after filter) rstin < 1032 tcl 4 tcl 4) 3) 12 tcl 1) 500 ns 50 ns 500 ns 50 ns 500 ns 50 ns ibus-cs 7 tcl 1. rstin assertion can be released there. refer also to section 21.1 for details on minimum pulse duration. 2. if during the reset condition (rstin low), rpd voltage dr ops below the threshold voltage (about 2.5v for 5v operation), the asynchronous reset is then immediately entered. 3. rstin pin is pulled low if bit bdrsten (bit 3 of syscon register) was previously set by software. bit bdrsten is cleared after reset. 4. minimum rstin low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1). notes: (internal) 8 tcl not t.
system reset st10f276 114/229 figure 29. synchronous short / long hardware reset (ea = 0) p0[15:13] not transparent rstf p0[12:2] transparent not t. p0[1:0] not t. not transparent rst 1024 tcl 3..8 tcl3) 2) vrpd > 2.5v asynchronous reset not entered 200ma discharge rpd rstout at this time rstf is sampled high or low so it is short or long reset (after filter) rstin < 1032 tcl 4 tcl5) 4) 12 tcl 1) 500 ns 50 ns 500 ns 50 ns 500 ns 50 ns ale 8 tcl 1. rstin assertion can be released there. refer also to section 21.1 for details on minimum pulse duration. 2. if during the reset condition (rstin low), rpd voltage drops below the threshold voltage (about 2.5v for 5v operation ) the asynchronous reset is then immediately entered. 4. rstin pin is pulled low if bit bdrsten (bit 3 of syscon register) was previously set by software. bit bdrsten is cleared after reset. 5. minimum rstin low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1). notes: 3. 3 to 8 tcl depending on clock source selection. 8 tcl not t.
st10f276 system reset 115/229 figure 30. synchronous long hardware reset (ea = 1) p0[15:13] not transparent rstf p0[12:2] transparent not t. p0[1:0] not t. not transparent flarst rst 1 ms 1024+8 tcl 2 tcl 1) v rpd > 2.5v asynchronous reset not entered 200 a discharge rpd rstout at this time rstf is sampled low so it is definitely long reset (after filter) rstin 1024+8 tcl 4 tcl 2) 12 tcl 500 ns 50 ns 500 ns 50 ns 500 ns 50 ns ibus-cs 7 tcl 1. if during the reset condition (rstin low), rpd voltage drops below the threshold voltage (about 2.5v for 5v operation), the asynchronous reset is then immediately entered. even if rpd returns above the threshold, 2. minimum rstin low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1). notes: not t. transparent not t. 3..4 tcl (internal) the reset is defnitively taken as asynchronous.
system reset st10f276 116/229 figure 31. synchronous long hardware reset (ea = 0) 19.4 software reset a software reset sequence can be triggered at any time by the protected srst (software reset) instruction. this instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals system failure. on execution of the srst instruction, the internal reset sequence is started. the microcontroller behavior is the same as for a synchronous short reset, except that only bits p0.12...p0.8 are latched at the end of the reset sequence, while previously latched, bits p0.7...p0.2 are cleared (that is written at ?1?). a software reset is always taken as synchronous: there is no influence on software reset behavior with rpd status. in case bidirectional reset is selected, a software reset event pulls rstin pin low: this occurs only if rpd is high; if rpd is low, rstin pin is not pulled low even though bidirect ional reset is selected. p0[15:13] not transparent rstf p0[12:2] transparent not t. p0[1:0] not t. not transparent rst 1024+8 tcl 3..8 tcl 3) 1) v rpd > 2.5v asynchronous reset not entered 200 a discharge rpd rstout at this time rstf is sampled low so it is long reset (after filter) rstin 1024+8 tcl 4 tcl 2) 12 tcl 500 ns 50 ns 500 ns 50 ns 500 ns 50 ns ale 8 tcl 1. if during the reset condition (rstin low), rpd voltage drops below the threshold voltage (about 2.5v for 5v operation), the asynchronous reset is then immediately entered. 2. minimum rstin low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1). notes: not t. transparent 3. 3 to 8 tcl depending on clock source selection. 3..4 tcl
st10f276 system reset 117/229 refer to next figures 32 and 33 for unidirectional sw reset timing, and to figures 34 , 35 and 36 for bidirectional. 19.5 watchdog timer reset when the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will over flow and trigger the reset sequence. unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use ready , or if ready is sampled active (low) after the programmed wait states. when ready is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. then the internal reset sequence is started. bit p0.12...p0.8 are latched at the end of the reset sequence and bit p0.7...p0.2 are cleared (that is written at ?1?). a watchdog reset is always taken as synchronous: there is no influence on watchdog reset behavior with rpd status. in case bidirectional reset is selected, a watchdog reset event pulls rstin pin low: this occurs only if rpd is high; if rpd is low, rstin pin is not pulled low even though bidirect ional reset is selected. refer to next figures 32 and 33 for unidirectional sw reset timing, and to figures 34 , 35 and 36 for bidirectional. figure 32. sw / wdt unidirectional reset (ea = 1) p0[7:2] not transparent p0[12:8] transparent not t. p0[1:0] not t. not transparent rst 1024 tcl rstout rstin ibus-cs 7 tcl p0[15:13] not transparent flarst 1 ms (internal) 2 tcl
system reset st10f276 118/229 figure 33. sw / wdt unidirectional reset (ea = 0) 19.6 bidirectional reset as shown in the previous sections, the rstout pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). rstout pin stays active low beyond the end of the initialization routine, until the protected einit instruct ion (end of initializ ation) is completed. the bidirectional reset function is useful when external devices require a reset signal but cannot be connected to rstout pin, because rstout signal lasts during initialization. it is, for instance, the case of external memo ry running initialization routine before the execution of einit instruction. bidirectional reset function is enabled by setting bit 3 (bdrsten) in syscon register. it only can be enabled during the initialization ro utine, before einit in struction is completed. when enabled, the open drain of the rstin pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). at the end of the internal reset sequence the pull down is released and: after a short synchronous bidirectional hardware reset, if rstf is sampled low 8 tcl periods after the internal reset sequence completion (refer to figure 28 and figure 29 ), the short reset becomes a long reset. on the contrary, if rstf is sampled high the device simply exits reset state. after a software or watchdog bidirectional reset, the device exits from reset. if rstf remains still low for at least 4 tcl periods (minimum time to recognize a short hardware reset) after the reset exiting (refer to figure 34 and figure 35 ), the software or watchdog reset become a short hardware reset. on the contrary, if rstf remains low for less than 4 tcl, the device simply exits reset state. p0[7:2] not transparent p0[12:8] transparent not t. p0[1:0] not t. not transparent rst 1024 tcl rstout rstin ale 8 tcl p0[15:13] not transparent
st10f276 system reset 119/229 the bidirectional reset is not effective in ca se rpd is held low, when a software or watchdog reset event occurs. on the contrary, if a software or watchdog bidirectional reset event is active and rpd becomes low, the rstin pin is immediately released, while the internal reset sequence is completed regardless of rpd status change (1024 tcl). note: the bidirectional reset function is disabled by any reset sequence (bit bdrsten of syscon is cleared). to be activated again it must be enabled during the initialization routine. wdtcon flags similarly to what already highlighted in the previous section when discussing about short reset and the degeneration into long reset, similar situations may occur when bidirectional reset is enabled. the presence of the internal filter on rstin pin introduces a delay: when rstin is released, the internal signal after the filter (see rstf in the drawings) is delayed, so it remains still active (low) for a while. it means that depending on the internal clock speed, a short reset may be recognized as a long reset: the wdtcon flags are set accordingly. besides, when either software or watchdog bidirectional reset events occur, again when the rstin pin is released (at the end of the internal reset sequence), the rstf internal signal (after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8tcl after the completion of the internal sequence, the level of rstf signal is sampled, and if recognized still low a hardware reset sequence starts, and wdtcon will flag this last event, masking the previous one (software or watchdog reset). typically, a short hardware reset is recognized, unless the rstin pin (and consequently internal signal rstf ) is sufficiently held low by the external hardware to inject a long hardware reset. after this occurrence, the init ialization routine is not able to recognize a software or watchdog bidirectional reset event, since a different source is flagged inside wdtcon register. this phenomenon does not occur when internal flash is selected during reset (ea = 1), since the initialization of the fl ash itself extend the internal reset duration well beyond the filter delay. next figures 34 , 35 and 36 summarize the timing for software and watchdog timer bidirectional reset events: in particular figure 36 shows the degeneration into hardware reset.
system reset st10f276 120/229 figure 34. sw / wdt bidirectional reset (ea =1) p0[15:13] not transparent rstf p0[12:8] transparent not t. p0[1:0] not t. not transparent rst 1024 tcl rstout (after filter) rstin 500 ns 50 ns 500 ns 50 ns ibus-cs 7 tcl flarst 1 ms 2 tcl (internal) p0[7:2] not transparent
st10f276 system reset 121/229 figure 35. sw / wdt bidirectional reset (ea = 0) p0[15:13] not transparent rstf p0[12:8] transparent not t. p0[1:0] not t. not transparent rst 1024 tcl rstout at this time rstf is sampled high so sw or wdt reset is flagged in wdtcon (after filter) rstin 500 ns 50 ns 500 ns 50 ns ale 8 tcl p0[7:2] not transparent
system reset st10f276 122/229 figure 36. sw / wdt bidirectional reset (ea =0) followed by a hw reset 19.7 reset circuitry internal reset circuitry is described in figure 39 . the rstin pin provides an internal pull-up resistor of 50k ? to 250k ? (the minimum reset time must be calculated using the lowest value). it also provides a programmable (bdrsten bit of syscon register) pull-down to output internal reset state signal (s ynchronous reset, watchdog timer reset or software reset). this bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to rstout pin. this is the case of an external memory runn ing codes before einit (e nd of initialization) instruction is executed. rstout pin is pulled high only when einit is executed. the rpd pin provides an internal weak pull-down resistor which discharges external capacitor at a typical rate of 200 a. if bit pwdcfg of syscon re gister is set, an internal pull-up resistor is activated at the end of th e reset sequence. this pull-up will charge any capacitor connected on rpd pin. the simplest way to reset the st10f276 is to insert a capacitor c1 between rstin pin and v ss , and a capacitor between rpd pin and v ss (c0) with a pull-up resistor r0 between rpd pin and v dd . the input rstin provides an internal pull-up device equalling a resistor of 50k ? to 250k ? (the minimum reset time must be determ ined by the lowest value). select c1 that produce a sufficient discha rge time to permit the internal or external oscillator and / or internal pll and the on-chip voltage regulator to stabilize. p0[15:13] not transparent rstf p0[12:8] transparent not t. p0[1:0] not t. not transparent rst 1024 tcl rstout at this time rstf is sampled low so hw reset is entered (after filter) rstin 500 ns 50 ns ale 8 tcl 500 ns 50 ns p0[7:2] not transparent
st10f276 system reset 123/229 to ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long peri od of time to stabilize, an as ynchronous hardware reset is required during power-up. for this reason, it is recommended to connect the external r0-c0 circuit shown in figure 37 to the rpd pin. on power-up, the logical low level on rpd pin forces an asynchronous hardware reset when rstin is asserted low. the external pull-up r0 will then charge the capacitor c0. note that an internal pull- down device on rpd pin is turned on when rstin pin is low, and causes the external capacitor (c0) to begin discharging at a typical rate of 100-200 a. with this mechanism, after power-up reset, short low pulses applied on rstin produce synchronous hardware reset. if rstin is asserted longer than the time needed for c0 to be discharged by the internal pull-down device, then the device is forced in an asynchronous reset. this mechanism insures recovery from very catastrophic failure. figure 37. minimum external reset circuitry the minimum reset circuit of figure 37 is not adequate when the rstin pin is driven from the st10f276 itself during software or watchdog triggered resets, because of the capacitor c1 that will keep the voltage on rstin pin above v il after the end of the internal reset sequence, and thus will trigger an asynchronous reset sequence. figure 38 shows an example of a reset circuit. in this example, r1-c1 external circuit is only used to generate power-up or manual reset, and r0-c0 circuit on rpd is used for power-up reset and to exit from power down mode. diode d1 creates a wired-or gate connection to the reset pin and may be replaced by open-collector schmitt trigger buffer. diode d2 provides a faster cycle time for repetitive power-on resets. r2 is an optional pull-up for faster recovery and correct biasing of ttl open collector drivers. rstout rpd rstin c1 a) hardware v cc + c0 r0 b) for power-up (and interruptible power down external hardware reset mode) reset + st10f276
system reset st10f276 124/229 figure 38. system reset circuit figure 39. internal (simplified) reset circuitry rpd rstin v dd + c0 r0 external hardware v dd r2 + c1 r1 d2 d1 o.d. external reset source open drain inverter v dd st10f276 rstout einit instruction trigger clr clock reset state machine internal reset signal reset sequence (512 cpu clock cycles) srst instruction watchdog overflow rstin v dd bdrsten v dd rpd weak pulldown (~200 a) from/to exit powerdown circuit asynchronous reset clr q set
st10f276 system reset 125/229 19.8 reset application examples next two timing diagrams ( figure 40 and figure 41 ) provides additional examples of bidirectional internal reset events (software and watchdog) including in particular the external capacitances charge and di scharge transients (refer also to figure 38 for the external circuit scheme). figure 40. example of software or watchdog bidirectional reset (ea = 1) vil vih rstout rstin rstf ideal tfilter rst < 500 ns 1024 tcl (12.8 us) 1 ms (c1 charge) tfilter rst < 500 ns rpd vil rst wdtcon [5:0] einit 04h 1ch 00h p0[15:13] < 4 tcl p0[12:8] p0[7:2] p0[1:0] latching point latching point latching point latching point not transparent not transparent not transparent not transparent not transparent not transparent not transparent not transparent transparent transparent transparent 4 tcl 3..8 tcl 0ch
system reset st10f276 126/229 figure 41. example of software or watchdog bidirectional reset (ea = 0) vil vih rstout rstin rstf ideal tfilter rst < 500 ns 1024 tcl (12.8 us) 1 ms (c1 charge) tfilter rst < 500 ns rpd vil rst wdtcon [5:0] einit 04h 1ch 00h p0[15:13] < 4 tcl p0[12:8] p0[7:2] p0[1:0] latching point latching point latching point latching point not transparent not transparent not transparent not transparent not transparent not transparent not transparent not transparent transparent transparent transparent 4 tcl 3..8 tcl 0ch
st10f276 system reset 127/229 19.9 reset summary a summary of the different reset events is reported in the table below. table 61. reset event event rpd ea bidir synch. asynch. rstin wdtcon flags min max ponr lhwr shwr swr wdtr power-on reset 0 0 n asynch. 1 ms (vreg) 1.2 ms (reson. + pll) 10.2 ms (crystal + pll) - 11110 0 1 n asynch. 1ms (vreg) - 1 1 1 1 0 1 x x forbidden x x y not applicable hardware reset (asynchronous) 0 0 n asynch. 500ns - 0 1 1 1 0 0 1 n asynch. 500ns - 0 1 1 1 0 0 0 y asynch. 500ns - 0 1 1 1 0 0 1 y asynch. 500ns - 0 1 1 1 0 short hardware reset (synchronous) (1) 1 0 n synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 1 1 n synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 1 0 y synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 activated by internal logic for 1024 tcl 1 1 y synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 activated by internal logic for 1024 tcl long hardware reset (synchronous) 1 0 n synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 1 1 n synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 1 0 y synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 activated by internal logic only for 1024 tcl 1 1 y synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 activated by internal logic only for 1024 tcl
system reset st10f276 128/229 the start-up configurations and some system features are selected on reset sequences as described in ta b l e 6 2 and figure 42 . ta bl e 6 2 describes what is the system configuration latched on port0 in the six different reset modes. figure 42 summarizes the state of bits of port0 latched in rp0h, syscon, buscon0 registers. software reset (2) x 0 n synch. not activated 0 0 0 1 0 x 0 n synch. not activated 0 0 0 1 0 0 1 y synch. not activated 0 0 0 1 0 1 1 y synch. activated by internal logic for 1024 tcl 0 0 0 1 0 watchdog reset (2) x 0 n synch. not activated 0 0 0 1 1 x 0 n synch. not activated 0 0 0 1 1 0 1 y synch. not activated 0 0 0 1 1 1 1 y synch. activated by internal logic for 1024 tcl 0 0 0 1 1 1. it can degenerate into a long hardware re set and consequently differently flagged (see section 19.3 for details). 2. when bidirectional is active (and with rpd=0), it can be followed by a sh ort hardware reset and consequently differently flagged (see section 19.6 for details). table 61. reset event (continued) event rpd ea bidir synch. asynch. rstin wdtcon flags min max ponr lhwr shwr swr wdtr table 62. port0 latched configuration for the different reset events x: pin is sampled -: pin is not sampled port0 clock options segm. addr. lines chip selects wr config. bus type reserved bsl reserved reserved adapt mode emu mode sample event p0h.7 p0h.6 p0h.5 p0h.4 p0h.3 p0h.2 p0h.1 p0h.0 p0l.7 p0l.6 p0l.5 p0l.4 p0l.3 p0l.2 p0l.1 p0l.0 software reset - - - xxxxxxx - - - - - - watchdog reset - - - xxxxxxx - - - - - - synchronous short hardware reset - - - xxxxxxxxxxxxx synchronous long hardware reset x x x x x x x x x x x x x x x x asynchronous hardware reset xxxxxxxxxxxxxxxx asynchronous power-on reset xxxxxxxxxxxxxxxx
st10f276 system reset 129/229 figure 42. port0 bits latched into the different registers after reset l.5 l.4 l.3 l.2 l.1 l.0 h.3 h.2 h.1 h.0 l.7 l.6 h.7 h.6 h.5 h.4 emu adp wrc cssel salsel bustyp rp0h clock port 4 logic port 6 logic syscon buscon0 internal control logic clkcfg 76 2 p0l.7 p0l.7 9 bytdis wrcfg port0 bootstrap loader generator clkcfg salsel cssel wrc btyp bsl res. 10 9 ale ctl0 bus act0 ea / vstby romen 10 8 7
power reduction modes st10f276 130/229 20 power reduction modes three different power reduction modes with different levels of power reduction have been implemented in the st10 f276. in idle mode only cpu is stopped, while peripheral still operate. in power down mode both cpu and peripherals are stopped. in stand-by mode the main power supply (v dd ) can be turned off while a portion of the internal ram remains powered via v stby dedicated power pin. idle and power down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections. stand-by mode is entered simply removing v dd , holding the mcu under reset state. note: all external bus actions are completed before idle or power down mode is entered. however, idle or power down mode is not entered if ready is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 20.1 idle mode idle mode is entered by running idle protected instruction. the cpu operation is stopped and the peripherals still run. idle mode is terminate by any interrupt request. whatever the interrupt is serviced or not, the instruction following the idle instruction will be executed after re turn from interrupt (reti) instruction, then the cpu resumes the normal program. 20.2 power down mode power down mode starts by running pwrdn protected instruction. internal clock is stopped, all mcu parts are on hold including the watchdog timer. the only exception could be the real time clock if opportunely progra mmed and one of the two oscillator circuits as a consequence (either the main or the 32 khz on-ch ip oscillator). when real time clock module is used, wh en the device is in power down mode a reference clock is needed. in this case, two possible configurations may be selected by the user application according to the desired level of power reduction: a 32 khz crystal is connected to the on-chi p low-power oscillator (pins xtal3 / xtal4) and running. in this case the main oscillator is stopped when power down mode is entered, while the real time clock continue counting using 32 khz clock signal as reference. the pr esence of a running low-power osc illator is detected after the power- on: this clock is immediately assumed (if pr esent, or as soon as it is detected) as reference for the real time clock counte r and it will be maintained forever (unless specifically disabled via software). only the main oscillator is running (xtal1 / xtal2 pins). in this case the main oscillator is not stopped when power down is entered, and the real time clock continue counting using the main o scillator clock signal as reference. there are two different operating power down modes: protected mode and interruptible mode.
st10f276 power reduction modes 131/229 before entering power down mode (by executing the instruction pwrdn), bit vregoff in xmisc register must be set. note: leaving the main voltage regulator active during power down may lead to unexpected behavior (ex: cpu wake-up) and power consumption higher than what specified. 20.2.1 protected power down mode this mode is selected when pwdcfg (bit 5) of syscon regist er is cleared. the protected power down mode is only activated if the nmi pin is pulled low when executing pwrdn instruction (this means that the pwrd instruction belongs to the nmi software routine). this mode is only deactivated with an external hardware reset on rstin pin. 20.2.2 interruptible power down mode this mode is selected when pwdcfg (b it 5) of syscon register is set. the interruptible power down mode is only activated if all the enabled fast external interrupt pins are in their inactive level. this mode is deactivated with an external reset applied to rstin pin or with an interrupt request applied to one of the fast external interrupt pins, or with an interrupt generated by the real time clock, or with an interrupt generated by the activity on can?s and i 2 c module interfaces. to allow t he internal pll and cloc k to stabilize, the rstin pin must be held low according the recommendations described in chapter 19: system reset . an external rc circuit must be connected to rpd pin, as shown in the figure 43 . figure 43. external rc circuitry on rpd pin to exit power down mode with an external interrupt, an exxin (x = 7...0) pin has to be asserted for at least 40ns. 20.3 stand-by mode in stand-by mode, it is possible to turn off the main v dd provided that v stby is available through the dedicated pin of the st10f276. to enter stand-by mode it is mandatory to held the device under reset: once the device is under reset, the ram is disabled (see xram2en bit of xpercon register), and its digital interface is frozen in order to avoid any kind of data corruption. a dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65v in stand-by mode) to bias all those circuits that shall remain active: the portion of xram (16kbytes for st10f273e), the rtc counters and 32 khz on- chip oscillator amplifier. rpd v dd c0 r0 220k ? minimum 1 f typical st10f276 +
power reduction modes st10f276 132/229 in normal running mode (that is when main v dd is on) the v stby pin can be tied to v ss during reset to exercise the ea functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with v stby (see in particular the 32 khz oscillator used in conjunction with real time clock module), is granted by the active main v dd . it must be noted that stand-by mode can generate problems associated with the usage of different power supplies in cmos systems; particular attention must be paid when the st10f276 i/o lines are interfaced with other external cmos integrated circuits: if v dd of st10f276 becomes (for example in stand-by mode) lower than the output level forced by the i/o lines of these external integrated circuits, the st10f276 could be directly powered through the inherent diode existing on st10f276 output driver circuitry. the same is valid for st10f276 interfaced to active/inactive communication buses during stand-by mode: current injection can be generated through the inherent diode. furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the st10f276 device). the device stand-by mode current (i stby ) may vary while v dd to v stby (and vice versa) transition occu rs: some current flows between v dd and v stby pins. system noise on both v dd and v stby can contribute to increase this phenomenon. 20.3.1 entering stand-by mode as already said, to enter stand-by mode xram2en bit in the xpercon register must be cleared: this allows to freeze immediately the ram interface, avoiding any data corruption. as a consequence of a reset event, the ram power supply is switched to the internal low-voltage supply v 18sb (derived from v stby through the low-power voltage regulator). the ram interface will remain frozen until t he bit xram2en is set again by software initialization routine (at next exit from main v dd power-on reset sequence). since v 18 is falling down (as a consequence of v dd turning off), it can happen that the xram2en bit is no longer able to guarantee its content (logic ?0?), being the xpercon register powered by internal v 18 . this does not generate any problem, because the stand- by mode switching dedicated circuit continues to confirm the ram interface freezing, irrespective the xram2en bit content; xram 2en bit status is considered again when internal v 18 comes back over internal stand-by reference v 18sb . if internal v 18 becomes lower than internal stand-by reference (v 18sb ) of about 0.3 to 0.45v with bit xram2en set, the ram supply switching circuit is not active: in case of a temporary drop on internal v 18 voltage versus internal v 18sb during normal code execution, no spurious stand-by mode switching can occur (the ram is not frozen and can still be accessed). the st10f276 core module, generating the ram control signals, is powered by internal v 18 supply; during turning off transient these control signals follow the v 18 , while ram is switched to v 18sb internal reference. it could happen that a high level of ram write strobe from st10f276 core (active low signal) is low enough to be recognized as a logic ?0? by the ram interface (due to v 18 lower than v 18sb ): the bus status could contain a valid address for the ram and an unwanted data corruption could occur. for this reason, an extra interface, powered by the switched supply, is used to prevent the ram from this kind of potential corruption mechanism.
st10f276 power reduction modes 133/229 warning: during power-off phase, it is important that the external hardware maintains a stable ground level on rstin pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. 20.3.2 exiting stand-by mode after the system has entered the stand-by mode, the procedure to exit this mode consists of a standard power-on sequence, with the only difference that the ram is already powered through v 18sb internal reference (derived from v stby pin external voltage). it is recommended to held th e device under reset (rstin pin forced low) until external v dd voltage pin is stable. even though, at the very beginning of the power-on phase, the device is maintained under reset by the inte rnal low voltage detector circuit (implemented inside the main voltage regu lator) till the internal v 18 becomes higher than about 1.0v, there is no warranty that the device stays under reset status if rstin is at high level during power ramp up. so, it is important the extern al hardware is able to guarantee a stable ground level on rstin along the power-on phase, without any temporary glitch. the external hardware shall be responsible to drive low the rstin pin until the v dd is stable, even though the internal lvd is active. once the internal reset signal goes low, the ra m (still frozen) power supply is switched to the main v 18 . at this time, everything becomes stable, and the execution of the initialization routines can start: xram2en bit can be set, enabling the ram. 20.3.3 real time cl ock and stand-by mode when stand-by mode is entered (turning off the main supply v dd ), the real time clock counting can be maintained running in case the on-chip 32 khz o scillator is used to provide the reference to the counter. this is not possible if th e main oscillator is used as reference for the counter: being the ma in oscillator powered by v dd , once this is switched off, the oscillator is stopped.
power reduction modes st10f276 134/229 20.3.4 power reduction modes summary in the following table 63: power reduction modes summary , a summary of the different power reduction modes is reported. table 63. power reduction modes summary mode v dd v stby cpu peripherals rtc main osc 32 khz osc stby xram xram idle on on off on off run off biased biased on on off on on run on biased biased power down on on off off off off off biased biased on on off off on on off biased biased on on off off on off on biased biased stand-by off on off off off off off biased off off on off off on off on biased off
st10f276 programmable output clock divider 135/229 21 programmable output clock divider a specific register mapped on the xbus allows to choose the division factor on the clkout signal (p3.15). this register is mapped on x-miscellaneous memory address range. when clkout function is enabled by setting bit clken of register syscon, by default the cpu clock is output on p3. 15. setting bit xmiscen of regi ster xpercon and bit xpen of register syscon, it is possible to program the clock prescaling factor: in this way on p3.15 a prescaled value of the cpu clock can be output. when clkout function is not enabled (bit clken of register syscon cleared), p3.15 does not output any clock signal, even though xclkoutdiv register is programmed.
register set st10f276 136/229 22 register set this section summarizes all registers implemented in the st10f276 and explains the description format used in the chapters to describe the function and layout of the sfrs. for easy reference, the registers (except for gprs) are sorted in two ways: ? sorted by address, to check which register is referenced by a given address. ? sorted by register name, to find the location of a specific register. 22.1 register description format throughout the document, the function and the layout of the different registers is described in a specific format. the example below explains this format. a word register is displayed as: a byte register is displayed as: elements: reg_name (a16h / a8h) sfr/esf r/xbus reset value: ****h: 1514131211109876543210 res. res. res. res. res. write only hw bit read only std bit hw bit bitfield bitfield w rw r rw rw rw rw table 64. description bit function bit(field) name explanation of bit(field) name description of the functions controlled by this bit(field). reg_name (a16h / a8h) sf r/esfr/xbus reset value: - - **h : 1514131211109876543210 --------std bithw bit bit field bit field rw rw rw rw reg_name this register?s name a16h / a8h long 16-bit address / short 8-bit address sfr / esfr/xbus register space (sfr, esfr or xbus register) (* *) * * register contents after reset 0/1 : defined x ?: undefined (undefined (? x ?) after power up) u ?: unchanged hwbit bit that is set/cleared by hardware is written in bold
st10f276 register set 137/229 22.2 general purpos e registers (gprs) the gprs form the register bank that the cpu works with. this register bank may be located anywhere within the internal ram via the context pointer (cp). due to the addressing mechanism, gpr banks reside only within the internal ram. all gprs are bit- addressable. the first 8 gprs (r7...r0) may also be accessed bytewise. other than with sfrs, writing to a gpr byte does not affect the other byte of the respective gpr. the respective halves of the byte-accessible registers have special names: table 65. general purpose registers (gprs) name physical address 8-bit addr ess description reset value r0 (cp) + 0 f0h cpu general purpose (word) register r0 uuuuh r1 (cp) + 2 f1h cpu general purpose (word) register r1 uuuuh r2 (cp) + 4 f2h cpu general purpose (word) register r2 uuuuh r3 (cp) + 6 f3h cpu general purpose (word) register r3 uuuuh r4 (cp) + 8 f4h cpu general purpose (word) register r4 uuuuh r5 (cp) + 10 f5h cpu general purpose (word) register r5 uuuuh r6 (cp) + 12 f6h cpu general purpose (word) register r6 uuuuh r7 (cp) + 14 f7h cpu general purpose (word) register r7 uuuuh r8 (cp) + 16 f8h cpu general purpose (word) register r8 uuuuh r9 (cp) + 18 f9h cpu general purpose (word) register r9 uuuuh r10 (cp) + 20 fah cpu general purpose (word) register r10 uuuuh r11 (cp) + 22 fbh cpu general purpose (word) register r11 uuuuh r12 (cp) + 24 fch cpu general purpose (word) register r12 uuuuh r13 (cp) + 26 fdh cpu general purpose (word) register r13 uuuuh r14 (cp) + 28 feh cpu general purpose (word) register r14 uuuuh r15 (cp) + 30 ffh cpu general purpose (word) register r15 uuuuh table 66. general purpose registers (gprs) bytewise addressing name physical address 8-bit address description reset value rl0 (cp) + 0 f0h cpu general purpose (byte) register rl0 uuh rh0 (cp) + 1 f1h cpu general purpose (byte) register rh0 uuh rl1 (cp) + 2 f2h cpu general purpose (byte) register rl1 uuh rh1 (cp) + 3 f3h cpu general purpose (byte) register rh1 uuh rl2 (cp) + 4 f4h cpu general purpose (byte) register rl2 uuh rh2 (cp) + 5 f5h cpu general purpose (byte) register rh2 uuh
register set st10f276 138/229 rl3 (cp) + 6 f6h cpu general purpose (byte) register rl3 uuh rh3 (cp) + 7 f7h cpu general purpose (byte) register rh3 uuh rl4 (cp) + 8 f8h cpu general purpose (byte) register rl4 uuh rh4 (cp) + 9 f9h cpu general purpose (byte) register rh4 uuh rl5 (cp) + 10 fah cpu general purpose (byte) register rl5 uuh rh5 (cp) + 11 fbh cpu general purpose (byte) register rh5 uuh rl6 (cp) + 12 fch cpu general purpose (byte) register rl6 uuh rh6 (cp) + 13 fdh cpu general purpose (byte) register rh6 uuh rl7 (cp) + 14 feh cpu general purpose (byte) register rl7 uuh rh7 (cp) + 15 ffh cpu general purpose (byte) register rh7 uuh table 66. general purpose registers (gprs) bytewise addressing name physical address 8-bit address description reset value rl0 (cp) + 0 f0h cpu general purpose (byte) register rl0 uuh
st10f276 register set 139/229 22.3 special function registers ordered by name the following table lists in alphabetical order all sfrs which are implemented in the st10f276. bit-addressable sfrs are marked with the letter ? b ? in column ?name?. sfrs within the extended sfr-space (esfrs) are marked with the letter ? e ? in column ?physical address?. table 67. special function registers ordered by address name physical address 8-bit address description reset value adcic b ff98h cch a/d converter end of conversion interrupt control register - - 00h adcon b ffa0h d0h a/d converter control register 0000h addat fea0h 50h a/d converter result register 0000h addat2 f0a0h e 50h a/d converter 2 result register 0000h addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h adeic b ff9ah cdh a/d converter overrun error interrupt control register - - 00h buscon0 b ff0ch 86h bus configuration register 0 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h caprel fe4ah 25h gpt2 capture/reload register 0000h cc0 fe80h 40h capcom register 0 0000h cc0ic b ff78h bch capcom register 0 interrupt control register - - 00h cc1 fe82h 41h capcom register 1 0000h cc10 fe94h 4ah capcom register 10 0000h cc10ic b ff8ch c6h capcom register 10 in terrupt control register - - 00h cc11 fe96h 4bh capcom register 11 0000h cc11ic b ff8eh c7h capcom register 11 in terrupt control register - - 00h cc12 fe98h 4ch capcom register 12 0000h cc12ic b ff90h c8h capcom register 12 in terrupt control register - - 00h cc13 fe9ah 4dh capcom register 13 0000h cc13ic b ff92h c9h capcom register 13 in terrupt control register - - 00h cc14 fe9ch 4eh capcom register 14 0000h
register set st10f276 140/229 cc14ic b ff94h cah capcom register 14 in terrupt control register - - 00h cc15 fe9eh 4fh capcom register 15 0000h cc15ic b ff96h cbh capcom register 15 in terrupt control register - - 00h cc16 fe60h 30h capcom register 16 0000h cc16ic b f160h e b0h capcom register 16 interr upt control register - - 00h cc17 fe62h 31h capcom register 17 0000h cc17ic b f162h e b1h capcom register 17 interr upt control register - - 00h cc18 fe64h 32h capcom register 18 0000h cc18ic b f164h e b2h capcom register 18 interr upt control register - - 00h cc19 fe66h 33h capcom register 19 0000h cc19ic b f166h e b3h capcom register 19 interr upt control register - - 00h cc1ic b ff7ah bdh capcom register 1 interrupt control register - - 00h cc2 fe84h 42h capcom register 2 0000h cc20 fe68h 34h capcom register 20 0000h cc20ic b f168h e b4h capcom register 20 interr upt control register - - 00h cc21 fe6ah 35h capcom register 21 0000h cc21ic b f16ah e b5h capcom register 21 interr upt control register - - 00h cc22 fe6ch 36h capcom register 22 0000h cc22ic b f16ch e b6h capcom register 22 interr upt control register - - 00h cc23 fe6eh 37h capcom register 23 0000h cc23ic b f16eh e b7h capcom register 23 interr upt control register - - 00h cc24 fe70h 38h capcom register 24 0000h cc24ic b f170h e b8h capcom register 24 interr upt control register - - 00h cc25 fe72h 39h capcom register 25 0000h cc25ic b f172h e b9h capcom register 25 interr upt control register - - 00h cc26 fe74h 3ah capcom register 26 0000h cc26ic b f174h e bah capcom register 26 interr upt control register - - 00h cc27 fe76h 3bh capcom register 27 0000h cc27ic b f176h e bbh capcom register 27 interr upt control register - - 00h cc28 fe78h 3ch capcom register 28 0000h cc28ic b f178h e bch capcom register 28 interr upt control register - - 00h cc29 fe7ah 3dh capcom register 29 0000h cc29ic b f184h e c2h capcom register 29 interr upt control register - - 00h cc2ic b ff7ch beh capcom register 2 interrupt control register - - 00h table 67. special function registers ordered by address (continued) name physical address 8-bit address description reset value
st10f276 register set 141/229 cc3 fe86h 43h capcom register 3 0000h cc30 fe7ch 3eh capcom register 30 0000h cc30ic b f18ch e c6h capcom register 30 interr upt control register - - 00h cc31 fe7eh 3fh capcom register 31 0000h cc31ic b f194h e cah capcom register 31 interr upt control register - - 00h cc3ic b ff7eh bfh capcom register 3 interrupt control register - - 00h cc4 fe88h 44h capcom register 4 0000h cc4ic b ff80h c0h capcom register 4 interrupt control register - - 00h cc5 fe8ah 45h capcom register 5 0000h cc5ic b ff82h c1h capcom register 5 interrupt control register - - 00h cc6 fe8ch 46h capcom register 6 0000h cc6ic b ff84h c2h capcom register 6 interrupt control register - - 00h cc7 fe8eh 47h capcom register 7 0000h cc7ic b ff86h c3h capcom register 7 interrupt control register - - 00h cc8 fe90h 48h capcom register 8 0000h cc8ic b ff88h c4h capcom register 8 interrupt control register - - 00h cc9 fe92h 49h capcom register 9 0000h cc9ic b ff8ah c5h capcom register 9 interrupt control register - - 00h ccm0 b ff52h a9h capcom mode control register 0 0000h ccm1 b ff54h aah capcom mode control register 1 0000h ccm2 b ff56h abh capcom mode control register 2 0000h ccm3 b ff58h ach capcom mode control register 3 0000h ccm4 b ff22h 91h capcom mode control register 4 0000h ccm5 b ff24h 92h capcom mode control register 5 0000h ccm6 b ff26h 93h capcom mode control register 6 0000h ccm7 b ff28h 94h capcom mode control register 7 0000h cp fe10h 08h cpu context pointer register fc00h cric b ff6ah b5h gpt2 caprel interrupt control register - - 00h csp fe08h 04h cpu code segment poin ter register (read-only) 0000h dp0h b f102h e 81h p0h direction control register - - 00h dp0l b f100h e 80h p0l direction control register - - 00h dp1h b f106h e 83h p1h direction control register - - 00h dp1l b f104h e 82h p1l direction control register - - 00h dp2 b ffc2h e1h port 2 direction control register 0000h table 67. special function registers ordered by address (continued) name physical address 8-bit address description reset value
register set st10f276 142/229 dp3 b ffc6h e3h port 3 direction control register 0000h dp4 b ffcah e5h port 4 direction control register - - 00h dp6 b ffceh e7h port 6 direction control register - - 00h dp7 b ffd2h e9h port 7 direction control register - - 00h dp8 b ffd6h ebh port 8 direction control register - - 00h dpp0 fe00h 00h cpu data page pointer 0 register (10-bit) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10-bit) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10-bit) 0002h dpp3 fe06h 03h cpu data page pointer 3 register (10-bit) 0003h emucon fe0ah 05h emulation control register - - xxh exicon b f1c0h e e0h external interrupt control register 0000h exisel b f1dah e edh external interrupt source selection register 0000h idchip f07ch e 3eh device identifier register (n is the device revision) 114nh idmanuf f07eh e 3fh manufacturer identifier register 0403h idmem f07ah e 3dh on-chip memory identifier register 30d0h idprog f078h e 3ch programming voltage identifier register 0040h idx0 b ff08h 84h mac unit address pointer 0 0000h idx1 b ff0ah 85h mac unit address pointer 1 0000h mah fe5eh 2fh mac unit accumulator - high word 0000h mal fe5ch 2eh mac unit accumulator - low word 0000h mcw b ffdch eeh mac unit control word 0000h mdc b ff0eh 87h cpu multiply divide control register 0000h mdh fe0ch 06h cpu multiply divide register ? high word 0000h mdl fe0eh 07h cpu multiply divide register ? low word 0000h mrw b ffdah edh mac unit repeat word 0000h msw b ffdeh efh mac unit status word 0200h odp2 b f1c2h e e1h port2 open drain control register 0000h odp3 b f1c6h e e3h port3 open drain control register 0000h odp4 b f1cah e e5h port4 open drain control register - - 00h odp6 b f1ceh e e7h port6 open drain control register - - 00h odp7 b f1d2h e e9h port7 open drain control register - - 00h odp8 b f1d6h e ebh port8 open drain control register - - 00h ones b ff1eh 8fh constant value 1?s register (read-only) ffffh p0h b ff02h 81h port0 high register (upper half of port0) - - 00h table 67. special function registers ordered by address (continued) name physical address 8-bit address description reset value
st10f276 register set 143/229 p0l b ff00h 80h port0 low register (lower half of port0) - - 00h p1h b ff06h 83h port1 high register (upper half of port1) - - 00h p1l b ff04h 82h port1 low register (lower half of port1) - - 00h p2 b ffc0h e0h port 2 register 0000h p3 b ffc4h e2h port 3 register 0000h p4 b ffc8h e4h port 4 register (8-bit) - - 00h p5 b ffa2h d1h port 5 register (read-only) xxxxh p5didis b ffa4h d2h port 5 digital disable register 0000h p6 b ffcch e6h port 6 register (8-bit) - - 00h p7 b ffd0h e8h port 7 register (8-bit) - - 00h p8 b ffd4h eah port 8 register (8-bit) - - 00h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h picon b f1c4h e e2h port input threshold control register - - 00h pp0 f038h e 1ch pwm module period register 0 0000h pp1 f03ah e 1dh pwm module period register 1 0000h pp2 f03ch e 1eh pwm module period register 2 0000h pp3 f03eh e 1fh pwm module period register 3 0000h psw b ff10h 88h cpu program status word 0000h pt0 f030h e 18h pwm module up/down counter 0 0000h pt1 f032h e 19h pwm module up/down counter 1 0000h pt2 f034h e 1ah pwm module up/down counter 2 0000h pt3 f036h e 1bh pwm module up/down counter 3 0000h pw0 fe30h 18h pwm module pulse width register 0 0000h pw1 fe32h 19h pwm module pulse width register 1 0000h pw2 fe34h 1ah pwm module pulse width register 2 0000h pw3 fe36h 1bh pwm module pulse width register 3 0000h pwmcon0 b ff30h 98h pwm module control register 0 0000h table 67. special function registers ordered by address (continued) name physical address 8-bit address description reset value
register set st10f276 144/229 pwmcon1 b ff32h 99h pwm module control register 1 0000h pwmic b f17eh e bfh pwm module interr upt control register - - 00h qr0 f004h e 02h mac unit offset register r0 0000h qr1 f006h e 03h mac unit offset register r1 0000h qx0 f000h e 00h mac unit offset register x0 0000h qx1 f002h e 01h mac unit offset register x1 0000h rp0h b f108h e 84h system start-up configuration register (read-only) - - xxh s0bg feb4h 5ah serial channel 0 baud rate generator reload register 0000h s0con b ffb0h d8h serial channel 0 control register 0000h s0eic b ff70h b8h serial channel 0 error interrupt control register - - 00h s0rbuf feb2h 59h serial channel 0 receive buffer register (read-only) - - xxh s0ric b ff6eh b7h serial channel 0 receive interrupt control register - - 00h s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control register - - 00h s0tbuf feb0h 58h serial channel 0 transmit buffer register (write-only) 0000h s0tic b ff6ch b6h serial channel 0 transmit interrupt control register - - 00h sp fe12h 09h cpu system stack pointer register fc00h sscbr f0b4h e 5ah ssc baud rate register 0000h ssccon b ffb2h d9h ssc control register 0000h ssceic b ff76h bbh ssc error interrupt control register - - 00h sscrb f0b2h e 59h ssc receive buffer (read-only) xxxxh sscric b ff74h bah ssc receive interrupt control register - - 00h ssctb f0b0h e 58h ssc transmit buffer (write-only) 0000h ssctic b ff72h b9h ssc transmit interrupt control register - - 00h stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h syscon b ff12h 89h cpu system configuration register 0xx0h t0 fe50h 28h capcom timer 0 register 0000h t01con b ff50h a8h capcom timer 0 and timer 1 control register 0000h t0ic b ff9ch ceh capcom timer 0 interrupt control register - - 00h t0rel fe54h 2ah capcom timer 0 reload register 0000h t1 fe52h 29h capcom timer 1 register 0000h t1ic b ff9eh cfh capcom timer 1 interrupt control register - - 00h t1rel fe56h 2bh capcom timer 1 reload register 0000h table 67. special function registers ordered by address (continued) name physical address 8-bit address description reset value
st10f276 register set 145/229 t2 fe40h 20h gpt1 timer 2 register 0000h t2con b ff40h a0h gpt1 timer 2 control register 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register - - 00h t3 fe42h 21h gpt1 timer 3 register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t3ic b ff62h b1h gpt1 timer 3 interrupt control register - - 00h t4 fe44h 22h gpt1 timer 4 register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t4ic b ff64h b2h gpt1 timer 4 interrupt control register - - 00h t5 fe46h 23h gpt2 timer 5 register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t5ic b ff66h b3h gpt2 timer 5 interrupt control register - - 00h t6 fe48h 24h gpt2 timer 6 register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t6ic b ff68h b4h gpt2 timer 6 in terrupt control register - - 00h t7 f050h e 28h capcom timer 7 register 0000h t78con b ff20h 90h capcom timer 7 and 8 control register 0000h t7ic b f17ah e bdh capcom timer 7 interrupt control register - - 00h t7rel f054h e 2ah capcom timer 7 reload register 0000h t8 f052h e 29h capcom timer 8 register 0000h t8ic b f17ch e beh capcom timer 8 interrupt control register - - 00h t8rel f056h e 2bh capcom timer 8 reload register 0000h tfr b ffach d6h trap flag register 0000h wdt feaeh 57h watchdog timer register (read-only) 0000h wdtcon b ffaeh d7h watchdog timer control register 00xxh xadrs3 f01ch e 0eh xper address select register 3 800bh xp0ic b f186h e c3h see section 8.1 - - 00h xp1ic b f18eh e c7h see section 8.1 - - 00h xp2ic b f196h e cbh see section 8.1 - - 00h xp3ic b f19eh e cfh see section 8.1 - - 00h xpercon f024h e 12h xper configuration register - - 05h zeros b ff1ch 8eh constant value 0?s register (read-only) 0000h table 67. special function registers ordered by address (continued) name physical address 8-bit address description reset value
register set st10f276 146/229 note: 1 the system configuration is selected during reset. syscon reset value is 0000 0xx0 x000 0000b. 2 reset value depends on different triggered reset event. 3 the xpnic interrupt control registers control interrupt requests from integrated x-bus peripherals. some software controlled interrupt requests may be generated by setting the xpnir bits (of xpnic register) of the unused x-peripheral nodes. 22.4 special function regi sters ordered by address the following table lists by order of their physical addresses all sfrs which are implemented in the st10f276 . bit-addressable sfrs are marked with the letter ? b ? in column ?name?. sfrs within the extended sfr-space (esfrs) are marked with the letter ? e ? in column ?physical address?. table 68. special function registers ordered by address name physical address 8-bit address description reset value qx0 f000h e 00h mac unit offset register x0 0000h qx1 f002h e 01h mac unit offset register x1 0000h qr0 f004h e 02h mac unit offset register r0 0000h qr1 f006h e 03h mac unit offset register r1 0000h xadrs3 f01ch e 0eh xper address select register 3 800bh xpercon f024h e 12h xper configuration register - - 05h pt0 f030h e 18h pwm module up/down counter 0 0000h pt1 f032h e 19h pwm module up/down counter 1 0000h pt2 f034h e 1ah pwm module up/down counter 2 0000h pt3 f036h e 1bh pwm module up/down counter 3 0000h pp0 f038h e 1ch pwm module period register 0 0000h pp1 f03ah e 1dh pwm module period register 1 0000h pp2 f03ch e 1eh pwm module period register 2 0000h pp3 f03eh e 1fh pwm module period register 3 0000h t7 f050h e 28h capcom timer 7 register 0000h t8 f052h e 29h capcom timer 8 register 0000h t7rel f054h e 2ah capcom timer 7 reload register 0000h t8rel f056h e 2bh capcom timer 8 reload register 0000h idprog f078h e 3ch programming voltage identifier register 0040h idmem f07ah e 3dh on-chip memory identifier register 30d0h idchip f07ch e 3eh device identifier register (n is the device revision) 114nh idmanuf f07eh e 3fh manufacturer identifier register 0403h
st10f276 register set 147/229 addat2 f0a0h e 50h a/d converter 2 result register 0000h ssctb f0b0h e 58h ssc transmit buffer (write-only) 0000h sscrb f0b2h e 59h ssc receive buffer (read-only) xxxxh sscbr f0b4h e 5ah ssc baud rate register 0000h dp0l b f100h e 80h p0l direction control register - - 00h dp0h b f102h e 81h p0h direction control register - - 00h dp1l b f104h e 82h p1l direction control register - - 00h dp1h b f106h e 83h p1h direction control register - - 00h rp0h b f108h e 84h system start-up configuration register (read-only) - - xxh cc16ic b f160h e b0h capcom register 16 interrupt control register - - 00h cc17ic b f162h e b1h capcom register 17 interrupt control register - - 00h cc18ic b f164h e b2h capcom register 18 interrupt control register - - 00h cc19ic b f166h e b3h capcom register 19 interrupt control register - - 00h cc20ic b f168h e b4h capcom register 20 interrupt control register - - 00h cc21ic b f16ah e b5h capcom register 21 interrupt control register - - 00h cc22ic b f16ch e b6h capcom register 22 interrupt control register - - 00h cc23ic b f16eh e b7h capcom register 23 interrupt control register - - 00h cc24ic b f170h e b8h capcom register 24 interrupt control register - - 00h cc25ic b f172h e b9h capcom register 25 interrupt control register - - 00h cc26ic b f174h e bah capcom register 26 interrupt control register - - 00h cc27ic b f176h e bbh capcom register 27 interrupt control register - - 00h cc28ic b f178h e bch capcom register 28 interrupt control register - - 00h t7ic b f17ah e bdh capcom timer 7 interrupt control register - - 00h t8ic b f17ch e beh capcom timer 8 interrupt control register - - 00h pwmic b f17eh e bfh pwm module interrupt control register - - 00h cc29ic b f184h e c2h capcom register 29 interrupt control register - - 00h xp0ic b f186h e c3h see section 8.1 - - 00h cc30ic b f18ch e c6h capcom register 30 interrupt control register - - 00h xp1ic b f18eh e c7h see section 8.1 - - 00h cc31ic b f194h e cah capcom register 31 interrupt control register - - 00h xp2ic b f196h e cbh see section 8.1 - - 00h s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control register. - - 00h xp3ic b f19eh e cfh see section 8.1 - - 00h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value
register set st10f276 148/229 exicon b f1c0h e e0h external interrupt control register 0000h odp2 b f1c2h e e1h port2 open drain control register 0000h picon b f1c4h e e2h port input threshold control register - - 00h odp3 b f1c6h e e3h port3 open drain control register 0000h odp4 b f1cah e e5h port4 open drain control register - - 00h odp6 b f1ceh e e7h port6 open drain control register - - 00h odp7 b f1d2h e e9h port7 open drain control register - - 00h odp8 b f1d6h e ebh port8 open drain control register - - 00h exisel b f1dah e edh external interrupt source selection register 0000h dpp0 fe00h 00h cpu data page pointer 0 register (10-bit) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10-bit) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10-bit) 0002h dpp3 fe06h 03h cpu data page pointer 3 register (10-bit) 0003h csp fe08h 04h cpu code segment pointer register (read-only) 0000h emucon fe0ah 05h emulation control register - - xxh mdh fe0ch 06h cpu multiply divide register ? high word 0000h mdl fe0eh 07h cpu multiply divide register ? low word 0000h cp fe10h 08h cpu context pointer register fc00h sp fe12h 09h cpu system stac k pointer register fc00h stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h pw0 fe30h 18h pwm module pulse width register 0 0000h pw1 fe32h 19h pwm module pulse width register 1 0000h pw2 fe34h 1ah pwm module pulse width register 2 0000h pw3 fe36h 1bh pwm module pulse width register 3 0000h t2 fe40h 20h gpt1 timer 2 register 0000h t3 fe42h 21h gpt1 timer 3 register 0000h t4 fe44h 22h gpt1 timer 4 register 0000h t5 fe46h 23h gpt2 timer 5 register 0000h t6 fe48h 24h gpt2 timer 6 register 0000h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value
st10f276 register set 149/229 caprel fe4ah 25h gpt2 capture/reload register 0000h t0 fe50h 28h capcom timer 0 register 0000h t1 fe52h 29h capcom timer 1 register 0000h t0rel fe54h 2ah capcom timer 0 reload register 0000h t1rel fe56h 2bh capcom timer 1 reload register 0000h mal fe5ch 2eh mac unit accumulator - low word 0000h mah fe5eh 2fh mac unit accumulator - high word 0000h cc16 fe60h 30h capcom register 16 0000h cc17 fe62h 31h capcom register 17 0000h cc18 fe64h 32h capcom register 18 0000h cc19 fe66h 33h capcom register 19 0000h cc20 fe68h 34h capcom register 20 0000h cc21 fe6ah 35h capcom register 21 0000h cc22 fe6ch 36h capcom register 22 0000h cc23 fe6eh 37h capcom register 23 0000h cc24 fe70h 38h capcom register 24 0000h cc25 fe72h 39h capcom register 25 0000h cc26 fe74h 3ah capcom register 26 0000h cc27 fe76h 3bh capcom register 27 0000h cc28 fe78h 3ch capcom register 28 0000h cc29 fe7ah 3dh capcom register 29 0000h cc30 fe7ch 3eh capcom register 30 0000h cc31 fe7eh 3fh capcom register 31 0000h cc0 fe80h 40h capcom register 0 0000h cc1 fe82h 41h capcom register 1 0000h cc2 fe84h 42h capcom register 2 0000h cc3 fe86h 43h capcom register 3 0000h cc4 fe88h 44h capcom register 4 0000h cc5 fe8ah 45h capcom register 5 0000h cc6 fe8ch 46h capcom register 6 0000h cc7 fe8eh 47h capcom register 7 0000h cc8 fe90h 48h capcom register 8 0000h cc9 fe92h 49h capcom register 9 0000h cc10 fe94h 4ah capcom register 10 0000h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value
register set st10f276 150/229 cc11 fe96h 4bh capcom register 11 0000h cc12 fe98h 4ch capcom register 12 0000h cc13 fe9ah 4dh capcom register 13 0000h cc14 fe9ch 4eh capcom register 14 0000h cc15 fe9eh 4fh capcom register 15 0000h addat fea0h 50h a/d converter result register 0000h wdt feaeh 57h watchdog timer register (read-only) 0000h s0tbuf feb0h 58h serial channel 0 transmit buffer register (write-only) 0000h s0rbuf feb2h 59h serial channel 0 receive buffer register (read-only) - - xxh s0bg feb4h 5ah serial channel 0 baud rate generator reload register 0000h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h p0l b ff00h 80h port0 low register (lower half of port0) - - 00h p0h b ff02h 81h port0 high register (upper half of port0) - - 00h p1l b ff04h 82h port1 low register (lower half of port1) - - 00h p1h b ff06h 83h port1 high register (upper half of port1) - - 00h idx0 b ff08h 84h mac unit address pointer 0 0000h idx1 b ff0ah 85h mac unit address pointer 1 0000h buscon0 b ff0ch 86h bus configuration register 0 0xx0h mdc b ff0eh 87h cpu multiply divide control register 0000h psw b ff10h 88h cpu program status word 0000h syscon b ff12h 89h cpu system c onfiguration register 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h zeros b ff1ch 8eh constant value 0?s register (read-only) 0000h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value
st10f276 register set 151/229 ones b ff1eh 8fh constant value 1?s register (read-only) ffffh t78con b ff20h 90h capcom timer 7 and 8 control register 0000h ccm4 b ff22h 91h capcom mode control register 4 0000h ccm5 b ff24h 92h capcom mode control register 5 0000h ccm6 b ff26h 93h capcom mode control register 6 0000h ccm7 b ff28h 94h capcom mode control register 7 0000h pwmcon0 b ff30h 98h pwm module control register 0 0000h pwmcon1 b ff32h 99h pwm module control register 1 0000h t2con b ff40h a0h gpt1 timer 2 control register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t01con b ff50h a8h capcom timer 0 and timer 1 control register 0000h ccm0 b ff52h a9h capcom mode control register 0 0000h ccm1 b ff54h aah capcom mode control register 1 0000h ccm2 b ff56h abh capcom mode control register 2 0000h ccm3 b ff58h ach capcom mode control register 3 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register - - 00h t3ic b ff62h b1h gpt1 timer 3 interrupt control register - - 00h t4ic b ff64h b2h gpt1 timer 4 interrupt control register - - 00h t5ic b ff66h b3h gpt2 timer 5 interrupt control register - - 00h t6ic b ff68h b4h gpt2 timer 6 interrupt control register - - 00h cric b ff6ah b5h gpt2 caprel interr upt control register - - 00h s0tic b ff6ch b6h serial channel 0 transmit interrupt control register - - 00h s0ric b ff6eh b7h serial channel 0 receive interrupt control register - - 00h s0eic b ff70h b8h serial channel 0 error interrupt control register - - 00h ssctic b ff72h b9h ssc transmit interrupt control register - - 00h sscric b ff74h bah ssc receive interrupt control register - - 00h ssceic b ff76h bbh ssc error interrupt control register - - 00h cc0ic b ff78h bch capcom register 0 interrupt control register - - 00h cc1ic b ff7ah bdh capcom register 1 in terrupt control register - - 00h cc2ic b ff7ch beh capcom register 2 in terrupt control register - - 00h cc3ic b ff7eh bfh capcom register 3 interrupt control register - - 00h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value
register set st10f276 152/229 cc4ic b ff80h c0h capcom register 4 interrupt control register - - 00h cc5ic b ff82h c1h capcom register 5 interrupt control register - - 00h cc6ic b ff84h c2h capcom register 6 interrupt control register - - 00h cc7ic b ff86h c3h capcom register 7 interrupt control register - - 00h cc8ic b ff88h c4h capcom register 8 interrupt control register - - 00h cc9ic b ff8ah c5h capcom register 9 interrupt control register - - 00h cc10ic b ff8ch c6h capcom register 10 interrupt control register - - 00h cc11ic b ff8eh c7h capcom register 11 interrupt control register - - 00h cc12ic b ff90h c8h capcom register 12 interrupt control register - - 00h cc13ic b ff92h c9h capcom register 13 interrupt control register - - 00h cc14ic b ff94h cah capcom register 14 interrupt control register - - 00h cc15ic b ff96h cbh capcom register 15 interrupt control register - - 00h adcic b ff98h cch a/d converter end of conversion interrupt control register - - 00h adeic b ff9ah cdh a/d converter overrun e rror interrupt control register - - 00h t0ic b ff9ch ceh capcom timer 0 interrupt control register - - 00h t1ic b ff9eh cfh capcom timer 1 inte rrupt control register - - 00h adcon b ffa0h d0h a/d converter control register 0000h p5 b ffa2h d1h port 5 register (read-only) xxxxh p5didis b ffa4h d2h port 5 digital disable register 0000h tfr b ffach d6h trap flag register 0000h wdtcon b ffaeh d7h watchdog timer control register 00xxh s0con b ffb0h d8h serial channel 0 control register 0000h ssccon b ffb2h d9h ssc control register 0000h p2 b ffc0h e0h port 2 register 0000h dp2 b ffc2h e1h port 2 direction control register 0000h p3 b ffc4h e2h port 3 register 0000h dp3 b ffc6h e3h port 3 direction control register 0000h p4 b ffc8h e4h port 4 register (8-bit) - - 00h dp4 b ffcah e5h port 4 direction control register - - 00h p6 b ffcch e6h port 6 register (8-bit) - - 00h dp6 b ffceh e7h port 6 direction control register - - 00h p7 b ffd0h e8h port 7 register (8-bit) - - 00h dp7 b ffd2h e9h port 7 direction control register - - 00h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value
st10f276 register set 153/229 22.5 x-registers sorted by name the following table lists by order of their names all x-bus registers which are implemented in the st10f276. although also physically mapped on x-bus memory space, the flash control registers are listed in a separate section, . note: the x-registers are not bit-addressable. p8 b ffd4h eah port 8 register (8-bit) - - 00h dp8 b ffd6h ebh port 8 direction control register - - 00h mrw b ffdah edh mac unit repeat word 0000h mcw b ffdch eeh mac unit control word 0000h msw b ffdeh efh mac unit status word 0200h table 68. special function registers ordered by address (continued) name physical address 8-bit address description reset value table 69. x-registers ordered by name name physical address description reset value can1brper ef0ch can1: brp extension register 0000h can1btr ef06h can1: bit timing register 2301h can1cr ef00h can1: can control register 0001h can1ec ef04h can1: error counter 0000h can1if1a1 ef18h can1: if1 arbitration 1 0000h can1if1a2 ef1ah can1: if1 arbitration 2 0000h can1if1cm ef12h can1: if1 command mask 0000h can1if1cr ef10h can1: if1 command request 0001h can1if1da1 ef1eh can1: if1 data a 1 0000h can1if1da2 ef20h can1: if1 data a 2 0000h can1if1db1 ef22h can1: if1 data b 1 0000h can1if1db2 ef24h can1: if1 data b 2 0000h can1if1m1 ef14h can1: if1 mask 1 ffffh can1if1m2 ef16h can1: if1 mask 2 ffffh can1if1mc ef1ch can1: if1 message control 0000h can1if2a1 ef48h can1: if2 arbitration 1 0000h can1if2a2 ef4ah can1: if2 arbitration 2 0000h can1if2cm ef42h can1: if2 command mask 0000h can1if2cr ef40h can1: if2 command request 0001h can1if2da1 ef4eh can1: if2 data a 1 0000h
register set st10f276 154/229 can1if2da2 ef50h can1: if2 data a 2 0000h can1if2db1 ef52h can1: if2 data b 1 0000h can1if2db2 ef54h can1: if2 data b 2 0000h can1if2m1 ef44h can1: if2 mask 1 ffffh can1if2m2 ef46h can1: if2 mask 2 ffffh can1if2mc ef4ch can1: if2 message control 0000h can1ip1 efa0h can1: interrupt pending 1 0000h can1ip2 efa2h can1: interrupt pending 2 0000h can1ir ef08h can1: interrupt register 0000h can1mv1 efb0h can1: message valid 1 0000h can1mv2 efb2h can1: message valid 2 0000h can1nd1 ef90h can1: new data 1 0000h can1nd2 ef92h can1: new data 2 0000h can1sr ef02h can1: status register 0000h can1tr ef0ah can1: test register 00x0h can1tr1 ef80h can1: transmission request 1 0000h can1tr2 ef82h can1: transmission request 2 0000h can2brper ee0ch can2: brp extension register 0000h can2btr ee06h can2: bit timing register 2301h can2cr ee00h can2: can control register 0001h can2ec ee04h can2: error counter 0000h can2if1a1 ee18h can2: if1 arbitration 1 0000h can2if1a2 ee1ah can2: if1 arbitration 2 0000h can2if1cm ee12h can2: if1 command mask 0000h can2if1cr ee10h can2: if1 command request 0001h can2if1da1 ee1eh can2: if1 data a 1 0000h can2if1da2 ee20h can2: if1 data a 2 0000h can2if1db1 ee22h can2: if1 data b 1 0000h can2if1db2 ee24h can2: if1 data b 2 0000h can2if1m1 ee14h can2: if1 mask 1 ffffh can2if1m2 ee16h can2: if1 mask 2 ffffh can2if1mc ee1ch can2: if1 message control 0000h can2if2a1 ee48h can2: if2 arbitration 1 0000h can2if2a2 ee4ah can2: if2 arbitration 2 0000h table 69. x-registers ordered by name (continued) name physical address description reset value
st10f276 register set 155/229 can2if2cm ee42h can2: if2 command mask 0000h can2if2cr ee40h can2: if2 command request 0001h can2if2da1 ee4eh can2: if2 data a 1 0000h can2if2da2 ee50h can2: if2 data a 2 0000h can2if2db1 ee52h can2: if2 data b 1 0000h can2if2db2 ee54h can2: if2 data b 2 0000h can2if2m1 ee44h can2: if2 mask 1 ffffh can2if2m2 ee46h can2: if2 mask 2 ffffh can2if2mc ee4ch can2: if2 message control 0000h can2ip1 eea0h can2: interrupt pending 1 0000h can2ip2 eea2h can2: interrupt pending 2 0000h can2ir ee08h can2: interrupt register 0000h can2mv1 eeb0h can2: message valid 1 0000h can2mv2 eeb2h can2: message valid 2 0000h can2nd1 ee90h can2: new data 1 0000h can2nd2 ee92h can2: new data 2 0000h can2sr ee02h can2: status register 0000h can2tr ee0ah can2: test register 00x0h can2tr1 ee80h can2: transmission request 1 0000h can2tr2 ee82h can2: transmission request 2 0000h i2cccr1 ea06h i2c clock control register 1 0000h i2cccr2 ea0eh i2c clock control register 2 0000h i2ccr ea00h i2c control register 0000h i2cdr ea0ch i2c data register 0000h i2coar1 ea08h i2c own address register 1 0000h i2coar2 ea0ah i2c own address register 2 0000h i2csr1 ea02h i2c status register 1 0000h i2csr2 ea04h i2c status register 2 0000h rtcah ed14h rtc alarm register high byte xxxxh rtcal ed12h rtc alarm register low byte xxxxh rtccon ed00h rtc control register 000xh rtcdh ed0ch rtc divider counter high byte xxxxh rtcdl ed0ah rtc divider counter low byte xxxxh rtch ed10h rtc programmable counter high byte xxxxh table 69. x-registers ordered by name (continued) name physical address description reset value
register set st10f276 156/229 rtcl ed0eh rtc programmable counter low byte xxxxh rtcph ed08h rtc prescaler register high byte xxxxh rtcpl ed06h rtc prescaler register low byte xxxxh xclkoutdiv eb02h clkout divider control register - - 00h xemu0 eb76h xbus emulation re gister 0 (write-only) xxxxh xemu1 eb78h xbus emulation re gister 1 (write-only) xxxxh xemu2 eb7ah xbus emulation register 2 (write-only) xxxxh xemu3 eb7ch xbus emulation re gister 3 (write-only) xxxxh xir0clr eb14h x-interrupt 0 clear register (write-only) 0000h xir0sel eb10h x-interrupt 0 selection register 0000h xir0set eb12h x-interrupt 0 set register (write-only) 0000h xir1clr eb24h x-interrupt 1 clear register (write-only) 0000h xir1sel eb20h x-interrupt 1 selection register 0000h xir1set eb22h x-interrupt 1 set register (write-only) 0000h xir2clr eb34h x-interrupt 2 clear register (write-only) 0000h xir2sel eb30h x-interrupt 2 selection register 0000h xir2set eb32h x-interrupt 2 set register (write-only) 0000h xir3clr eb44h x-interrupt 3 clear selection register (write- only) 0000h xir3sel eb40h x-interrupt 3 selection register 0000h xir3set eb42h x-interrupt 3 set selection register (write- only) 0000h xmisc eb46h xbus miscellaneous features register 0000h xp1didis eb36h port 1 digital disable register 0000h xperemu eb7eh xpercon copy for emulation (write-only) xxxxh xpicon eb26h extended port input threshold control register - - 00h xpolar ec04h xpwm module channel polarity register 0000h xpp0 ec20h xpwm module period register 0 0000h xpp1 ec22h xpwm module period register 1 0000h xpp2 ec24h xpwm module period register 2 0000h xpp3 ec26h xpwm module period register 3 0000h xpt0 ec10h xpwm module up/down counter 0 0000h xpt1 ec12h xpwm module up/down counter 1 0000h xpt2 ec14h xpwm module up/down counter 2 0000h table 69. x-registers ordered by name (continued) name physical address description reset value
st10f276 register set 157/229 xpt3 ec16h xpwm module up/down counter 3 0000h xpw0 ec30h xpwm module pulse width register 0 0000h xpw1 ec32h xpwm module pulse width register 1 0000h xpw2 ec34h xpwm module pulse width register 2 0000h xpw3 ec36h xpwm module pulse width register 3 0000h xpwmcon0 ec00h xpwm module control register 0 0000h xpwmcon0clr ec08h xpwm module clear control reg. 0 (write- only) 0000h xpwmcon0set ec06h xpwm module set control register 0 (write- only) 0000h xpwmcon1 ec02h xpwm module control register 1 0000h xpwmcon1clr ec0ch xpwm module clear control reg. 0 (write- only) 0000h xpwmcon1set ec0ah xpwm module set control register 0 (write- only) 0000h xpwmport ec80h xpwm module port control register 0000h xs1bg e906h xasc baud rate generator reload register 0000h xs1con e900h xasc control register 0000h xs1conclr e904h xasc clear control register (write-only) 0000h xs1conset e902h xasc set control register (write-only) 0000h xs1port e980h xasc port control register 0000h xs1rbuf e90ah xasc receive buffer register 0000h xs1tbuf e908h xasc transmit buffer register 0000h xsscbr e80ah xssc baud rate register 0000h xssccon e800h xssc control register 0000h xsscconclr e804h xssc clear control register (write-only) 0000h xsscconset e802h xssc set control register (write-only) 0000h xsscport e880h xssc port control register 0000h xsscrb e808h xssc receive buffer xxxxh xssctb e806h xssc transmit buffer 0000h table 69. x-registers ordered by name (continued) name physical address description reset value
register set st10f276 158/229 22.6 x-registers ordered by address the following table lists by order of their physical addresses all x-bus registers which are implemented in the st10f276. although also physically mapped on x-bus memory space, the flash control registers are listed in a separate section, . note: the x-registers are not bit-addressable. table 70. x-registers ordered by address name physical address description reset value xssccon e800h xssc control register 0000h xsscconset e802h xssc set control register (write-only) 0000h xsscconclr e804h xssc clear control register (write-only) 0000h xssctb e806h xssc transmit buffer 0000h xsscrb e808h xssc receive buffer xxxxh xsscbr e80ah xssc baud rate register 0000h xsscport e880h xssc port control register 0000h xs1con e900h xasc control register 0000h xs1conset e902h xasc set control register (write-only) 0000h xs1conclr e904h xasc clear control register (write-only) 0000h xs1bg e906h xasc baud rate generator reload register 0000h xs1tbuf e908h xasc transmit buffer register 0000h xs1rbuf e90ah xasc receive buffer register 0000h xs1port e980h xasc port control register 0000h i2ccr ea00h i2c control register 0000h i2csr1 ea02h i2c status register 1 0000h i2csr2 ea04h i2c status register 2 0000h i2cccr1 ea06h i2c clock control register 1 0000h i2coar1 ea08h i2c own address register 1 0000h i2coar2 ea0ah i2c own address register 2 0000h i2cdr ea0ch i2c data register 0000h i2cccr2 ea0eh i2c clock control register 2 0000h xclkoutdiv eb02h clkout divider control register - - 00h xir0sel eb10h x-interrupt 0 selection register 0000h xir0set eb12h x-interrupt 0 set register (write-only) 0000h xir0clr eb14h x-interrupt 0 clear register (write-only) 0000h xir1sel eb20h x-interrupt 1 selection register 0000h xir1set eb22h x-interrupt 1 set register (write-only) 0000h xir1clr eb24h x-interrupt 1 clear register (write-only) 0000h
st10f276 register set 159/229 xpicon eb26h extended port input threshold control register - - 00h xir2sel eb30h x-interrupt 2 selection register 0000h xir2set eb32h x-interrupt 2 set register (write-only) 0000h xir2clr eb34h x-interrupt 2 clear register (write-only) 0000h xp1didis eb36h port 1 digital disable register 0000h xir3sel eb40h x-interrupt 3 selection register 0000h xir3set eb42h x-interrupt 3 set selection register (write-only) 0000h xir3clr eb44h x-interrupt 3 clear selection register (write-only) 0000h xmisc eb46h xbus miscellaneous features register 0000h xemu0 eb76h xbus emulation register 0 (write-only) xxxxh xemu1 eb78h xbus emulation register 1 (write-only) xxxxh xemu2 eb7ah xbus emulation register 2 (write-only) xxxxh xemu3 eb7ch xbus emulation register 3 (write-only) xxxxh xperemu eb7eh xpercon copy for emulation (write-only) xxxxh xpwmcon0 ec00h xpwm module control register 0 0000h xpwmcon1 ec02h xpwm module control register 1 0000h xpolar ec04h xpwm module channel polarity register 0000h xpwmcon0set ec06h xpwm module set control register 0 (write-only) 0000h xpwmcon0clr ec08h xpwm module clear control reg. 0 (write-only) 0000h xpwmcon1set ec0ah xpwm module set control register 0 (write-only) 0000h xpwmcon1clr ec0ch xpwm module clear control reg. 0 (write-only) 0000h xpt0 ec10h xpwm module up/down counter 0 0000h xpt1 ec12h xpwm module up/down counter 1 0000h xpt2 ec14h xpwm module up/down counter 2 0000h xpt3 ec16h xpwm module up/down counter 3 0000h xpp0 ec20h xpwm module period register 0 0000h xpp1 ec22h xpwm module period register 1 0000h xpp2 ec24h xpwm module period register 2 0000h xpp3 ec26h xpwm module period register 3 0000h xpw0 ec30h xpwm module pulse width register 0 0000h table 70. x-registers ordered by address (continued) name physical address description reset value
register set st10f276 160/229 xpw1 ec32h xpwm module pulse width register 1 0000h xpw2 ec34h xpwm module pulse width register 2 0000h xpw3 ec36h xpwm module pulse width register 3 0000h xpwmport ec80h xpwm module port control register 0000h rtccon ed00h rtc control register 000xh rtcpl ed06h rtc prescaler register low byte xxxxh rtcph ed08h rtc prescaler register high byte xxxxh rtcdl ed0ah rtc divider counter low byte xxxxh rtcdh ed0ch rtc divider counter high byte xxxxh rtcl ed0eh rtc programmable counter low byte xxxxh rtch ed10h rtc programmable counter high byte xxxxh rtcal ed12h rtc alarm register low byte xxxxh rtcah ed14h rtc alarm register high byte xxxxh can2cr ee00h can2: can control register 0001h can2sr ee02h can2: status register 0000h can2ec ee04h can2: error counter 0000h can2btr ee06h can2: bit timing register 2301h can2ir ee08h can2: interrupt register 0000h can2tr ee0ah can2: test register 00x0h can2brper ee0ch can2: brp extension register 0000h can2if1cr ee10h can2: if1 command request 0001h can2if1cm ee12h can2: if1 command mask 0000h can2if1m1 ee14h can2: if1 mask 1 ffffh can2if1m2 ee16h can2: if1 mask 2 ffffh can2if1a1 ee18h can2: if1 arbitration 1 0000h can2if1a2 ee1ah can2: if1 arbitration 2 0000h can2if1mc ee1ch can2: if1 message control 0000h can2if1da1 ee1eh can2: if1 data a 1 0000h can2if1da2 ee20h can2: if1 data a 2 0000h can2if1db1 ee22h can2: if1 data b 1 0000h can2if1db2 ee24h can2: if1 data b 2 0000h can2if2cr ee40h can2: if2 command request 0001h can2if2cm ee42h can2: if2 command mask 0000h can2if2m1 ee44h can2: if2 mask 1 ffffh table 70. x-registers ordered by address (continued) name physical address description reset value
st10f276 register set 161/229 can2if2m2 ee46h can2: if2 mask 2 ffffh can2if2a1 ee48h can2: if2 arbitration 1 0000h can2if2a2 ee4ah can2: if2 arbitration 2 0000h can2if2mc ee4ch can2: if2 message control 0000h can2if2da1 ee4eh can2: if2 data a 1 0000h can2if2da2 ee50h can2: if2 data a 2 0000h can2if2db1 ee52h can2: if2 data b 1 0000h can2if2db2 ee54h can2: if2 data b 2 0000h can2tr1 ee80h can2: transmission request 1 0000h can2tr2 ee82h can2: transmission request 2 0000h can2nd1 ee90h can2: new data 1 0000h can2nd2 ee92h can2: new data 2 0000h can2ip1 eea0h can2: interrupt pending 1 0000h can2ip2 eea2h can2: interrupt pending 2 0000h can2mv1 eeb0h can2: message valid 1 0000h can2mv2 eeb2h can2: message valid 2 0000h can1cr ef00h can1: can control register 0001h can1sr ef02h can1: status register 0000h can1ec ef04h can1: error counter 0000h can1btr ef06h can1: bit timing register 2301h can1ir ef08h can1: interrupt register 0000h can1tr ef0ah can1: test register 00x0h can1brper ef0ch can1: brp extension register 0000h can1if1cr ef10h can1: if1 command request 0001h can1if1cm ef12h can1: if1 command mask 0000h can1if1m1 ef14h can1: if1 mask 1 ffffh can1if1m2 ef16h can1: if1 mask 2 ffffh can1if1a1 ef18h can1: if1 arbitration 1 0000h can1if1a2 ef1ah can1: if1 arbitration 2 0000h can1if1mc ef1ch can1: if1 message control 0000h can1if1da1 ef1eh can1: if1 data a 1 0000h can1if1da2 ef20h can1: if1 data a 2 0000h can1if1db1 ef22h can1: if1 data b 1 0000h can1if1db2 ef24h can1: if1 data b 2 0000h table 70. x-registers ordered by address (continued) name physical address description reset value
register set st10f276 162/229 can1if2cr ef40h can1: if2 command request 0001h can1if2cm ef42h can1: if2 command mask 0000h can1if2m1 ef44h can1: if2 mask 1 ffffh can1if2m2 ef46h can1: if2 mask 2 ffffh can1if2a1 ef48h can1: if2 arbitration 1 0000h can1if2a2 ef4ah can1: if2 arbitration 2 0000h can1if2mc ef4ch can1: if2 message control 0000h can1if2da1 ef4eh can1: if2 data a 1 0000h can1if2da2 ef50h can1: if2 data a 2 0000h can1if2db1 ef52h can1: if2 data b 1 0000h can1if2db2 ef54h can1: if2 data b 2 0000h can1tr1 ef80h can1: transmission request 1 0000h can1tr2 ef82h can1: transmission request 2 0000h can1nd1 ef90h can1: new data 1 0000h can1nd2 ef92h can1: new data 2 0000h can1ip1 efa0h can1: interrupt pending 1 0000h can1ip2 efa2h can1: interrupt pending 2 0000h can1mv1 efb0h can1: message valid 1 0000h can1mv2 efb2h can1: message valid 2 0000h table 70. x-registers ordered by address (continued) name physical address description reset value
st10f276 register set 163/229 22.7 flash registers ordered by name the following table lists by order of their names all flash control registers which are implemented in the st10f276. note that as they are physically mapped on the x-bus, these registers are not bit-addressable. table 71. flash registers ordered by name name physical address description reset value farh 0x000e 0012 flash address register high 0000h farl 0x000e 0010 flash address register low 0000h fcr0h 0x000e 0002 flash control register 0 - high 0000h fcr0l 0x000e 0000 flash control register 0 - low 0000h fcr1h 0x000e 0006 flash control register 1 - high 0000h fcr1l 0x000e 0004 flash control register 1 - low 0000h fdr0h 0x000e 000a flash data register 0 - high ffffh fdr0l 0x000e 0008 flash data register 0 - low ffffh fdr1h 0x000e 000e flash data register 1 - high ffffh fdr1l 0x000e 000c flash data register 1 - low ffffh fer 0x000e 0014 flash error register 0000h fnvapr0 0x000e dfb8 flash nonvolatile access protection reg. 0 acffh fnvapr1h 0x000e dfbe flash nonvolatile access protection reg. 1 - high ffffh fnvapr1l 0x000e dfbc flash nonvolatile access protection reg. 1 - low ffffh fnvwpirh 0x000e dfb6 flash nonvolatile protection i reg. high ffffh fnvwpirl 0x000e dfb4 flash nonvolatile protection i reg. low ffffh fnvwpxrh 0x000e dfb2 flash nonvolatile protection x reg. high ffffh fnvwpxrl 0x000e dfb0 flash nonvolatile protection x reg. low ffffh xficr 0x000e e000 xflash interface control register 000fh
register set st10f276 164/229 22.8 flash registers ordered by address the following table lists by order of their physical addresses all flash control registers which are implemented in the st10f276. note that as they are physically mapped on the x- bus, these registers are not bit-addressable. table 72. flash registers ordered by address name physical address description reset value fcr0l 0x000e 0000 flash control register 0 - low 0000h fcr0h 0x000e 0002 flash control register 0 - high 0000h fcr1l 0x000e 0004 flash control register 1 - low 0000h fcr1h 0x000e 0006 flash control register 1 - high 0000h fdr0l 0x000e 0008 flash data register 0 - low ffffh fdr0h 0x000e 000a flash data register 0 - high ffffh fdr1l 0x000e 000c flash data register 1 - low ffffh fdr1h 0x000e 000e flash data register 1 - high ffffh farl 0x000e 0010 flash address register low 0000h farh 0x000e 0012 flash address register high 0000h fer 0x000e 0014 flash error register 0000h fnvwpxrl 0x000e dfb0 flash nonvolatile protection x reg. low ffffh fnvwpxrh 0x000e dfb2 flash nonvolatile protection x reg. high ffffh fnvwpirl 0x000e dfb4 flash nonvolat ile protection i reg. low ffffh fnvwpirh 0x000e dfb6 flash nonvolat ile protection i reg. high ffffh fnvapr0 0x000e dfb8 flash nonvolatile access protection reg. 0 acffh fnvapr1l 0x000e dfbc flash nonvolatile access protection reg. 1 - low ffffh fnvapr1h 0x000e dfbe flash nonvolatile access protection reg. 1 - high ffffh xficr 0x000e e000 xflash interface control register 000fh
st10f276 register set 165/229 22.9 identification registers the st10f276 have four identification registers, mapped in esfr space. these registers contain: ? the manufacturer identifier ? the chip identifier with revision number ? the internal flash and size identifier ? the programming voltage description idmanuf (f07eh / 3fh) esfr reset value:0403h 1514131211109876543210 manuf 00011 r table 73. manuf description bit function manuf manufacturer identifier 020h: stmicroelectronics manufactur er (jtag worldwide normalization) idchip (f07ch / 3eh) esfr reset value:114xh 1514131211109876543210 idchip revid rr table 74. idchip description bit function idchip device identifier 114h: st10f276 identifier (276) revid device revision identifier xh: according to revision number idmem (f07ah / 3dh) esfr reset value:30d0h 1514131211109876543210 memtyp memsize rr
register set st10f276 166/229 note: all identification words are read-only registers. the values written inside different identification register bits are valid only after the flash initialization phase is completed. when code execution is started from internal memory (pin ea held high during reset), the flash has completed its initialization, so the bits of identification registers are immediately ready to be read out. on the contrary, when code execution is started from external memory (pin ea held low during reset), the flash initialization is not yet complete d, so the bits of identification registers are not ready. the user can poll bits 15 and 14 of idmem register: when both bits are read low, the flash initialization is complete, so all iden tification register bits are correct. before flash initialization completion, the default setting of the different identification registers are the following: table 75. idmem description bit function memsize internal memory size internal memory size is 4 x (memsize) (in kbyte) 0d0h for st10f276 (832 kbytes) memtyp internal memory type ?0h?: rom-less ?1h?: (m) rom memory ?2h?: (s) standard flash memory ?3h?: (h) high performance flash memory (st10f276) ?4h...fh?: reserved idprog (f078h / 3ch) esfr reset value:0040h 1514131211109876543210 progvpp progvdd rr table 76. idprog description bit function progvdd programming vdd voltage vdd voltage when programming eprom or flash devices is calculated using the following formula: vdd = 20 x [progvdd] / 256 (volts) - 40h for st10f276 (5v). progvpp programming vpp voltage ( no need of external vpp) - 00h idmanuf 0403h idchip 114xh (x = silicon revision) idmem f0d0h idprog 0040h
st10f276 register set 167/229 22.10 system configuration registers the st10f276 has registers used for a different configuration of the overall system. these registers are described below. note: syscon reset value is: 0000 0xx0 0x00 0000b . syscon (ff12h / 89h) sfr reset value: 0xx0h 1514131211109876543210 stksz rom s1 sgt dis rom en byt dis clk en wr cfg cs cfg pwd cfg owd dis bdr sten xpen visi ble xper- share rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 77. syscon description bit function xper-share xbus peripheral share mode control ?0?: external accesses to xbus peripherals are disabled. ?1?: xram1 and xram2 are accessible via the external bus during hold mode. external accesses to the other xbus peripherals are not guaranteed in terms of ac timings. visible visible mode control ?0?: accesses to xbus peripherals are done internally. ?1?: xbus peripheral accesses are made visible on the external pins. xpen xbus peripheral enable bit ?0?: accesses to the on-chip x-peripherals and xram are disabled. ?1?: the on-chip x-peripherals are enabled. bdrsten bidirectional reset enable ?0?: rstin pin is an input pin only. sw reset or wdt reset have no effect on this pin. ?1?: rstin pin is a bidirectional pin. this pin is pulled low during internal reset sequence. owddis oscillator watchdog disable control ?0?: oscillator watchdog (owd) is enabled. if pll is bypassed, the owd monitors xtal1 activity. if there is no activity on xtal1 for at least 1 s, the cpu clock is switched automatically to pll?s base frequency (from 750 khz to 3 mhz). ?1?: owd is disabled. if the pll is bypa ssed, the cpu clock is always driven by xtal1 signal. the pll is turned off to reduce power supply current. pwdcfg power down mode configuration control ?0?: power down mode can only be entered during pwrdn instruction execution if nmi pin is low, otherwise th e instruction has no effect. to exit power down mode, an external reset must occur by asserting the rstin pin. ?1?: power down mode can only be entered during pwrdn instruction execution if all enabled fast external interrupt exxin pins are in their inactive level. exiting this mode can be done by asserting one enabled exxin pin or with external reset. cscfg chip select configuration control ?0?: latched chip select lines, csx changes 1 tcl after rising edge of ale. ?1?: unlatched chip select lines, csx changes with rising edge of ale.
register set st10f276 168/229 wrcfg write configuration control (inverted copy of wrc bit of rp0h) ?0?: pins wr and bhe retain their normal function. ?1?: pin wr acts as wrl, pin bhe acts as wrh. clken system clock output enable (clkout) ?0?: clkout disabled, pin may be used for general purpose i/o. ?1?: clkout enabled, pin ou tputs the system clock signal or a prescaled value of system clock according to xc lkoutdiv register setting. bytdis disable/enable control for pin bhe (set according to data bus width) ?0?: pin bhe enabled. ?1?: pin bhe disabled, pin may be used for general purpose i/o. romen internal memory enable (set according to pin ea during reset) ?0?: internal memory disa bled: accesses to the ifla sh memory area use the external bus. ?1?: internal memory enabled. sgtdis segmentation disable/enable control ?0?: segmentation enabled (csp is saved/ restored during interrupt entry/exit). ?1?: segmentation disabled (only ip is saved/restored). roms1 internal memory mapping ?0?: internal memory area mapped to segment 0 (00?0000h...00?7fffh). ?1?: internal memory area mapped to segment 1 (01?0000h...01?7fffh). stksz system stack size selects the size of the system stack (in the internal i-ram) from 32 to 1024 words. buscon0 (ff0ch / 86h) sfr reset value: 0xx0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cswen0 csren0 rdypol0 rdyen0 - busact0 alectl0 - btyp mttc0 rwdc0 mctc rw rw rw rw rw rw rw rw rw buscon1 (ff14h / 8ah) sfr reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cswen1 csren1 rdypol1 rdyen1 - busact1 alectl1 - btyp mttc1 rwdc1 mctc rw rw rw rw rw rw rw rw rw rw buscon2 (ff16h / 8bh) sfr reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cswen2 csren2 rdypol2 rdyen2 - busact2 alectl2 - btyp mttc2 rwdc2 mctc rw rw rw rw rw rw rw rw rw buscon3 (ff18h / 8ch) sfr reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cswen3 csren3 rdypol3 rdyen3 - busact3 alectl3 - btyp mttc3 rwdc3 mctc rw rw rw rw rw rw rw rw rw table 77. syscon desc ription (continued) bit function
st10f276 register set 169/229 buscon4 (ff1ah / 8dh) sfr reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cswen4 csren4 rdypol4 rdyen4 - busact4 alectl4 - btyp mttc4 rwdc4 mctc rw rw rw rw rw rw rw rw rw table 78. buscon4 description bit function mctc memory cycle time control (number of memory cycle time wait-states) ?0000?: 15 wait-states (number of wait-states = 15 - [mctc]). . . . ?1111?: no wait-states. rwdcx read/write delay control for busconx ?0?: with read/write delay, the cpu inserts 1 tcl after falling edge of ale. ?1?: no read/write delay, rw is activated after falling edge of ale. mttcx memory tristate time control ?0?: 1 wait-state. ?1?: no wait-state. btyp external bus configuration ?00?: 8-bit demultiplexed bus ?01?: 8-bit multiplexed bus ?10?: 16-bit demultiplexed bus ?11?: 16-bit multiplexed bus note: for buscon0 btyp is defined via port0 during reset. alectlx ale lengthening control ?0?: normal ale signal. ?1?: lengthened ale signal. busactx bus active control ?0?: external bus disabled. ?1?: external bus enabled (within the respective address window, see addrsel). rdyenx ready input enable ?0?: external bus cycle is cont rolled by bit field mctc only. ?1?: external bus cycle is controlled by the ready input signal. rdypolx ready active level control ?0?: active level on the ready pin is low, bus cycle terminates with a ?0? on ready pin. ?1?: active level on the ready pin is high, bus cycle terminates with a ?1? on ready pin. csrenx read chip select enable ?0?: the cs signal is independent of the read command (rd ). ?1?: the cs signal is generated for the duration of the read command. cswenx write chip select enable ?0?: the cs signal is independent of the write command (wr , wrl , wrh ). ?1?: the cs signal is generated for the duration of the write command.
register set st10f276 170/229 note: 1 btyp (bit 6 and 7) is set according to the configuration of the bit l6 and l7 of port0 latched at the end of the reset sequence. 2 buscon0 is initialized with 0000h, if ea pin is high during reset. if ea pin is low during reset, bit busact0 and alectrl0 are set (?1?) and bit field btyp is loaded with the bus configuration selected via port0. rp0h (f108h / 84h) esfr reset value: --xxh 1514131211109876543210 - clksel salsel cssel wrc r r r r table 79. rpoh description (1) 1. rp0h is a read -only register. bit function wrc (2) write configuration control ?0?: pin wr acts as wrl , pin bhe acts as wrh ?1?: pins wr and bhe retain their normal function cssel (2) chip select line selection (number of active cs outputs) 0 0: 3 cs lines: cs 2...cs 0 0 1: 2 cs lines: cs 1...cs 0 1 0: no cs line at all 1 1: 5 cs lines: cs 4...cs 0 (default without pull-downs) salsel (2) 2. these bits are set according to port 0 configuration dur ing any reset sequence. segment address line selection (number of active segment address outputs) ?00?: 4-bit segment address: a19...a16 ?01?: no segment address lines at all ?10?: 8-bit segment address: a23...a16 ?11?: 2-bit segment address: a17. ..a16 (default without pull-downs) clksel (2) (3) 3. rp0h.7 to rp0h.5 bits are loaded only during a long hardware reset. as pull-up resistors are active on each port p0h pins during reset, rp0h default value is ?ffh?. system clock selection ?000?: f cpu = 16 x f osc ?001?: f cpu = 0.5 x f osc ?010?: f cpu = 10 x f osc ?011?: f cpu = f osc ?100?: f cpu = 5 x f osc ?101?: f cpu = 8 x f osc ?110?: f cpu = 3 x f osc ?111?: f cpu = 4 x f osc exicon (f1c0h / e0h) esfr reset value: 0000h 1514131211109876543210 exi7es exi6es exi5es exi4es exi3es exi2es exi1es exi0es rw rw rw rw rw rw rw rw
st10f276 register set 171/229 note: 1. xp3ic register has the same bit field as xxic interrupt registers table 80. exixes bit description bit function exixes (x=7...0) 00 = fast external interrupts disabled: standard mode. exxin pin not taken in account for entering/exiting power down mode. 01 = interrupt on positive edge (rising). enter power down mode if exiin = ?0?, exit if exxin = ?1? (referred as "high" active level) 10 = interrupt on negative edge (falling). enter power down mode if exiin = ?1?, exit if exxin = ?0? (referred as ?low? active level) 11 = interrupt on any edge (rising or falling). always enter power down mode, exit if exxin level changed. exisel (f1dah / edh) esfr reset value: 0000h 1514131211109876543210 exi7ss exi6ss exi5ss exi4ss exi3ss exi2ss exi1ss exi0ss rw rw rw rw rw rw rw rw table 81. exisel bit function exixss external interrupt x source selection (x = 7...0) 00 = input from associated port 2 pin. 01 = input from ?alternate source?. 10 = input from port 2 pin ored with ?alternate source?. 11 = input from port 2 pin anded with ?alternate source?. table 82. exixss and port 2 pin configurations exixss port 2 pin alternate source 0 p2.8 can1_rxd 1 p2.9 can2_rxd / scl 2 p2.10 rtcsi (second) 3 p2.11 rtcai (alarm) 4...7 p2.12...15 not used (zero) xp3ic (f19eh / cfh) esfr reset value: --00h 1514131211109876543210 -------- xp3ir xp3ie xp3ilvl glvl rw rw rw rw xxic (yyyyh / zzh) sfr area reset value: --00h 1514131211109876543210 --------xxirxxie ilvl glvl rw rw rw rw
register set st10f276 172/229 table 83. sfr area description bit function glvl group level defines the internal order for simultaneous requests of the same priority. ?3?: highest group priority ?0?: lowest group priority ilvl interrupt priority level defines the priority level for the arbitration of requests. ?fh?: highest priority level ?0h?: lowest priority level xxie interrupt enable control bit (individually enables/disables a specific source) ?0?: interrupt request is disabled ?1?: interrupt request is enabled xxir interrupt request flag ?0?: no request pending ?1?: this source has raised an interrupt request xpercon (f024h / 12h) esfr reset value:- 005h 1514131211109876543210 ----- xmisc en xi2c en xssc en xasc en xpwm en xflas hen xrtc en xram2 en xram1 en can2 en can1 en - - - - - rw rw rw rw rw rw rw rw rw rw rw table 84. esfr description bit function can1en can1 enable bit ?0?: accesses to the on-chip can1 xperipheral and its functions are disabled (p4.5 and p4.6 pins can be used as general purpose i/os, but address range 00?ec00h- 00?efffh is directed to external me mory only if can2en, xrtcen, xascen, xsscen, xi2cen, xpwmen an xmiscen are ?0? also). ?1?: the on-chip can1 xperipheral is enabled and can be accessed. can2en can2 enable bit ?0?: accesses to the on-chip can2 xperipheral and its functions are disabled (p4.4 and p4.7 pins can be used as general purpose i/os, but address range 00?ec00h- 00?efffh is directed to external me mory only if can1en, xrtcen, xascen, xsscen, xi2cen, xpwmen and xmiscen are ?0? also). ?1?: the on-chip can2 xperipheral is enabled and can be accessed. xram1en xram1 enable bit ?0?: accesses to the on-chip 2 kbyte xram are disabled. address range 00?e000h-00?e7ffh is directed to external memory. ?1?: the on-chip 2 kbyte xram is enabled and can be accessed. xram2en xram2 enable bit ?0?: accesses to the on-chip 64 kbyte xram are disabled, external access performed. address range 0f?0000h-0f?ffffh is directed to external memory only if xflashen is ?0? also. ?1?: the on-chip 64 kbyte xram is enabled and can be accessed.
st10f276 register set 173/229 when can1, can2, rtc, xasc, xssc, i 2 c, xpwm and the xbus additional features are all disabled via xpercon setting, then any access in the address range 00?e800h - 00?efffh is directed to external memory interface, using the busconx register corresponding to the address matching addrselx register. all pins used for x-peripherals can be used as general purpose i/o whenever the related module is not enabled. xrtcen rtc enable ?0?: accesses to the on-chip rtc module are disabled, external access performed. address range 00?ed00h-00?edff is directed to external memory only if can1en, can2en, xascen, xsscen, xi2cen, xpwmen and xmiscen are ?0? also. ?1?: the on-chip rtc module is enabled and can be accessed. xpwmen xpwm enable ?0?: accesses to the on-chip xpwm module are disabled, external access performed. address range 00?ec00h-00?ecff is directed to external memory only if can1en, can2en, xascen, xsscen, xi2cen, xrtcen and xmiscen are ?0? also. ?1?: the on-chip xpwm module is enabled and can be accessed. xflashen xflash enable bit ?0?: accesses to the on-chip xflash and flash registers are disabled, external access performed. address range 09?0000h-0e?ffffh is directed to external memory only if xram2en is ?0? also. ?1?: the on-chip xflash is enabled and can be accessed. xascen xasc enable bit ?0?: accesses to the on-chip xasc are disabled, external access performed. address range 00?e900h-00?e9ffh is di rected to external memory only if can1en, can2en, xrtcen, xascen, xi2cen, xpwmen and xmiscen are ?0? also. ?1?: the on-chip xasc is enabled and can be accessed. xsscen xssc enable bit ?0?: accesses to the on-chip xssc are disabled, external access performed. address range 00?e800h-00?e8ffh is di rected to external memory only if can1en, can2en, xrtcen, xascen, xi2cen, xpwmen and xmiscen are ?0? also. ?1?: the on-chip xssc is enabled and can be accessed. xi2cen i 2 c enable bit ?0?: accesses to the on-chip i 2 c are disabled, external access performed. address range 00?ea00h-00?eaffh is directed to external memory only if can1en, can2en, xrtcen, xascen, xsscen, xpwmen and xmiscen are ?0? also. ?1?: the on-chip i 2 c is enabled and can be accessed. xmiscen xbus additional features enable bit ?0?: accesses to the additional miscellaneous features is disabled. address range 00?eb00h-00?ebffh is directed to external memory only if can1en, can2en, xrtcen, xascen, xsscen, xpwmen and xi2cen are ?0? also. ?1?: the additional features are enabled and can be accessed. table 84. esfr description (continued) bit function
register set st10f276 174/229 the default xper selection after reset is such that can1 is enabled, can2 is disabled, xram1 (2 kbyte xram) is enabled and xram2 (64 kbyte xram) is disabled; all the other x-peripherals are disabled after reset. register xpercon cannot be changed after the global enabling of x-peripherals, that is, after setting of bit xpen in syscon register. in emulation mode, all the x-peripherals ar e enabled (xpercon bits are all set). the bondout chip determines whether or not to redirect an access to external memory or to xbus. reserved bits of xpercon regist er are always written to ?0?. ta bl e 8 5 below summarizes the segment 8 mapping that depends upon the ea pin status during reset as well as the syscon (b it xpen) and xpercon (bits xram2en and xflashen) registers user programmed values. . note: the symbol ?x? in the table above stands for ?do not care?. 22.10.1 xpercon and xpe remu registers as already mentioned, the xpercon register must be programmed to enable the single xbus modules separately. the xpercon is a read/write esfr register; the xperemu register is a write-only register mapped on xbus memory space (address eb7eh). once the xpen bit of syscon register is set and at least one of the x-peripherals (except memories) is activated, the register xperemu must be written with the same content of xpercon: this is mandatory in order to allow a correct em ulation of th e new set of features introduced on xbus for the new st10 generation. the following instructions must be added inside the initialization routine: if (syscon.xpen && (xpercon & 0x07d3)) then { xperemu = xpercon } of course, xperemu must be programmed after xpercon and afte r syscon; in this way the final configuration for x-peripherals is stored in xperemu and used for the emulation hardware setup. note: the bit meaning is exactly the same as in xpercon. table 85. segment 8 address range mapping ea xpen xram2en xflashen segment 8 0 0 x x external memory 0100external memory 0 1 1 x reserved 01x1reserved 1 x x x iflash (b1f1) xperemu (eb7eh) xbus reset value xxxxh: 1514131211109876543210 ----- xmisc en xi2c en xssc en xasc en xpwm en xflas hen xrtc en xram2 en xram1 en can2 en can1 en - - - - - rw rw rw rw rw rw rw rw rw rw rw
st10f276 register set 175/229 22.11 emulation dedicated registers four additional registers are implemented for emulation purposes only. similarly to xperemu, they are write-only registers. xemu0 (eb76h) xbus reset value: xxxxh 1514131211109876543210 xemu0(15:0) w xemu1 (eb78h) xbus reset value: xxxxh 1514131211109876543210 xemu1(15:0) w xemu2 (eb7ah) xbus reset value: xxxxh: 1514131211109876543210 xemu2(15:0) w xemu3 (eb7ch) xbus reset value: xxxxh 1514131211109876543210 xemu3(15:0) w
electrical characteristics st10f276 176/229 23 electrical characteristics 23.1 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. during overload conditions (v in > v dd or v in < v ss ) the voltage on pins with respect to ground (v ss ) must not exceed the values defined by the absolute maximum ratings. during power-on and power-off transients (including stand-by entering/exiting phases), the relationships between voltages applied to the device and the main v dd must always be respected. in particular, power-on and power-off of v aref must be coherent with the v dd transient, in order to avoid undesired current injection through the on-chip protection diodes. 23.2 recommended op erating conditions table 86. absolute maximum ratings symbol parameter value unit v dd voltage on v dd pins with respect to ground (v ss ) - 0.3 to +6.5 v v stby voltage on v stby pin with respect to ground (v ss ) v aref voltage on v aref pin with respect to ground (v ss ) - 0.3 to v dd + 0.3 v agnd voltage on v agnd pin with respect to ground (v ss )v ss v io voltage on any pin with respect to ground (v ss ) - 0.5 to v dd + 0.5 i ov input current on any pin during overload condition 10 ma i tov absolute sum of all input currents during overload condition | 75 | t st storage temperature - 65 to +150 c esd esd susceptibility (human body model) 2000 v table 87. recommended operating conditions symbol parameter min. max. unit v dd operating supply voltage 4.5 5.5 v v stby operating stand-by supply voltage (1) 1. the value of the v stby voltage is specified in the range 4.5 - 5. 5 volts. nevertheless, it is acceptable to exceed the upper limit (up to 6.0 volts) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device (about 30 years) . on the other hand, it is possible to exceed the lower limit (down to 4.0 volts) whenever rtc and 32 kh z on-chip oscillator amplif ier are turned off (only stand-by ram powered through v stby pin in stand-by mode). when v stby voltage is lower than main v dd , the input section of v stby /ea pin can generate a spurious static consumption on v dd power supply (in the range of tenth of a). v aref operating analog reference voltage (2) 0 v dd t a ambient temperature under bias ?40 +125 c t j junction temperature under bias +150
st10f276 electrical characteristics 177/229 23.3 power considerations the average chip-junction temperature, t j , in degrees celsius, is calculated using the following equation: t j = t a + (p d x ja ) 1) where: t a is the ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o (p d = p int + p i/o ), p int is the product of i dd and v dd , expressed in watt. this is the chip internal power, p i/o represents the power dissipation on input and output pins; user determined. most often in applications, p i/o < p int ,which may be ignored. on the other hand, p i/o may be significant if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273c) + ja x p d 2 (3) where: k is a constant for the particular part, which may be determined from equation (3) by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j are obtained by solving equations (1) and (2) iteratively for any value of t a . based on thermal characteristics of the package and with reference to the power consumption figures provided in the next tables and diagrams, the following product classification can be proposed. in any case , the exact power consumption of the device inside the application must be computed according to different working conditions, thermal profiles, real thermal resistance of the system (including printed circuit board or other substrata) and i/o activity. 2. for details on operating c onditions concerning the usage of a/d converter, refer to section 23.7 . table 88. thermal characteristics symbol description value (typical) unit ja thermal resistance junction-ambient pqfp 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch lqfp 144 - 20 x 20 mm / 0.5 mm pitch lqfp 144 - 20 x 20 mm / 0.5 mm pitch on four layer fr4 board (2 layers signals / 2 layers power) 30 40 35 c/w
electrical characteristics st10f276 178/229 23.4 parameter interpretation the parameters listed in the following tables represent the characteristics of the st10f276 and its demands on the system. where the st10f276 logic provides signals with their respective timing characteristics, the symbol ?cc? (controller characteristics) is included in the ?symbol? column. where the external system must provide signals with their respective timing characteristics to the st10f276, the symbol ?sr? (system requirement) is included in the ?symbol? column. 23.5 dc characteristics v dd = 5v 10%, v ss = 0v, t a = ?40 to +125c table 89. package characteristics package operating temperature cpu frequency range die - 40 / +125 c 1 ? 64 mhz pqfp 144 lqfp 144 1 ? 40 mhz lqfp 144 -40/+105c 1 ? 48 mhz table 90. dc characteristics symbol parameter test condition limit values unit min. max. v il sr input low voltage (ttl mode) (except rstin , ea , nmi , rpd, xtal1, ready) ? ? 0.3 0.8 v v ils sr input low voltage (cmos mode) (except rstin , ea , nmi , rpd, xtal1, ready) ? ? 0.3 0.3 v dd v il1 sr input low voltage rstin , ea , nmi , rpd ? ? 0.3 0.3 v dd v il2 sr input low voltage xtal1 (cmos only) direct drive mode ? 0.3 0.3 v dd v il3 sr input low voltage ready (ttl only) ? ? 0.3 0.8 v ih sr input high voltage (ttl mode) (except rstin , ea , nmi , rpd, xtal1) ?2.0v dd + 0.3 v ihs sr input high voltage (cmos mode) (except rstin , ea , nmi , rpd, xtal1) ? 0.7 v dd v dd + 0.3 v ih1 sr input high voltage rstin , ea , nmi , rpd ? 0.7 v dd v dd + 0.3
st10f276 electrical characteristics 179/229 v ih2 sr input high voltage xtal1 (cmos only) direct drive mode 0.7 v dd v dd + 0.3 v v ih3 sr input high voltage ready (ttl only) ?2.0v dd + 0.3 vhys cc input hysteresis (ttl mode) (except rstin , ea , nmi , xtal1, rpd) 3) 400 700 mv vhyss cc input hysteresis (cmos mode) (except rstin , ea , nmi , xtal1, rpd) 3) 750 1400 vhys1 cc input hysteresis rstin , ea , nmi 3) 750 1400 vhys2 cc input hysteresis xtal1 3) 0 50 vhys3 cc input hysteresis ready (ttl only) 3) 400 700 vhys4 cc input hysteresis rpd 3) 500 1500 v ol cc output low voltage (p6[7:0], ale, rd , wr /wrl , bhe /wrh , clkout, rstin , rstout ) i ol = 8 ma i ol = 1 ma ? 0.4 0.05 v v ol1 cc output low voltage (p0[15:0], p1[15:0], p2[15:0], p3[15,13:0], p4[7:0], p7[7:0], p8[7:0]) i ol1 = 4 ma i ol1 = 0.5 ma ? 0.4 0.05 v ol2 cc output low voltage rpd i ol2 = 85 a i ol2 = 80 a i ol2 = 60 a ? v dd 0.5 v dd 0.3 v dd v oh cc output high voltage (p6[7:0], ale, rd , wr /wrl , bhe /wrh , clkout, rstout ) i oh = ? 8 ma i oh = ? 1 ma v dd ? 0.8 v dd ? 0.08 ? v oh1 cc output high voltage (1) (p0[15:0], p1[15:0], p2[15:0], p3[15,13:0], p4[7:0], p7[7:0], p8[7:0]) i oh1 = ? 4 ma i oh1 = ? 0.5 ma v dd ? 0.8 v dd ? 0.08 ? v oh2 cc output high voltage rpd i oh2 = ? 2 ma i oh2 = ? 750 a i oh2 = ? 150 a 0 0.3 v dd 0.5 v dd ? | i oz1 | cc input leakage current (p5[15:0]) (2) ??0.2 a | i oz2 | cc input leakage current (all except p5[15:0], p2.0, rpd) ??0.5 | i oz3 | cc input leakage current (p2.0) (3) ?? +1.0 ?0.5 | i oz4 | cc input leakage current (rpd) ? ? 3.0 | i ov1 | sr overload current (all except p2.0) (4) (5) ?5ma table 90. dc characteristics (continued) symbol parameter test condition limit values unit min. max.
electrical characteristics st10f276 180/229 | i ov2 | sr overload current (p2.0) (3) (4)(5) ? +5 ?1 ma r rst cc rstin pull-up resistor 100 k ? nominal 50 250 k ? i rwh read/write inactive current (6) (7) v out = 2.4 v ? ?40 a i rwl read/write active current (6)(8) v out = 0.4v ?500 ? i alel ale inactive current (6) (7) v out = 0.4v 20 ? i aleh ale active current (6) (8) v out = 2.4 v ? 300 i p6h port 6 inactive current (p6[4:0]) (6)(7) v out = 2.4 v ? ?40 i p6l port 6 active current (p6[4:0]) (6) (8) v out = 0.4v ?500 ? i p0h 6) port0 configuration current (6) v in = 2.0v ? ?10 i p0l 7) v in = 0.8v ?100 ? c io cc pin capacitance (digital inputs / outputs) (4)(6) ?10pf i cc1 run mode power supply current (9) (execution from internal ram) ? ? 20 + 2 f cpu ma i cc2 run mode power supply current (4)(10) (execution from internal flash) ?? 20 + 1.8 f cpu ma i id idle mode supply current (11) ?? 20 + 0.6 f cpu ma i pd1 power down supply current (12) (rtc off, oscillators off, main voltage regulator off) t a = 25c ? 1 ma i pd2 power down supply current (12) (rtc on, main oscillator on, main voltage regulator off) t a = 25c ? 8 ma i pd3 power down supply current (12) (rtc on, 32 khz oscillator on, main voltage regulator off) t a = 25c ? 1.1 ma i sb1 stand-by supply current (12) (rtc off, oscillators off, vdd off, vstby on) v stby = 5.5v t a = t j = 25c ? 250 a v stby = 5.5v t a = t j = 125c ? 500 a i sb2 stand-by supply current (12) (rtc on, 32 khz oscillator on, main vdd off, vstby on) v stby = 5.5v t a = 25c ? 250 a v stby = 5.5v t a = 125c ? 500 a i sb3 stand-by supply current (4) (12) (vdd transient condition) ??2.5ma table 90. dc characteristics (continued) symbol parameter test condition limit values unit min. max.
st10f276 electrical characteristics 181/229 1. this specification is not valid for outputs which are switched to open drain mode. in this case the respective output floats and the voltag e is imposed by the external circuitry. 2. port 5 leakage values are granted for not sele cted a/d converter channel. one channels is always selected (by default, after reset, p5.0 is selected). for the selected channel the leakage value is similar to that of other port pins. 3. the leakage of p2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes) implemented on input path. pay attention to not stress p2.0 input pin with negative overload beyond the specified limits: failures in flash reading may occur (sense am plifier perturbation). refer to next figure 44 for a scheme of the input circuitry. 4. not 100% tested, guaranteed by design characterization. 5. overload conditions occur if the standard operati ng conditions are exceeded, that is, the voltage on any pin exceeds the specif ied range (that is, v ov > v dd + 0.3v or v ov < ?0.3v). the absolute sum of input overload currents on all port pins may not exceed 50m a. the supply voltage must remain within the specified limits. 6. this specification is only valid dur ing reset, or during hold- or adapt-mode. port 6 pins are only affected if they are used for cs output and the open drain function is not enabled. 7. the maximum current may be drawn while the respective signal li ne remains inactive. 8. the minimum current must be drawn in order to drive the respecti ve signal line active. 9. the power supply current is a f unction of the operating frequency (f cpu is expressed in mhz). this dependency is illustrated in the figure 45 below. this parameter is tested at v ddmax and at maximum cpu clock frequency with all outputs disconnected and all inputs at v il or v ih , rstin pin at v ih1min : this implies i/o current is not considered . the device is doing the following: - fetching code from iram and xram1, acce ssing in read and write to both xram modules - watchdog timer is enabled and regularly serviced - rtc is running with main oscillator clock as refer ence, generating a tick interrupts every 192 clock cycles - four channels of xpwm are running (w aves period: 2, 2.5, 3 and 4 cpu cl ock cycles): no output toggling - five general purpose timers are running in timer mode with prescaler equal to 8 (t2, t3, t4, t5, t6) - adc is in auto scan continuous conv ersion mode on all 16 channels of port5 - all interrupts generated by xpwm, rt c, timers and adc are not serviced 10. the power supply current is a f unction of the operating frequency (f cpu is expressed in mhz). this dependency is illustrated in the figure 45 below. this parameter is tested at v ddmax and at maximum cpu clock frequency with all outputs disconnected and all inputs at v il or v ih , rstin pin at v ih1min : this implies i/o current is not considered . the device is doing the following: - fetching code from all sectors of both iflash and xf lash, accessing in read (few fetches) and write to xram - watchdog timer is enabled and regularly serviced - rtc is running with main oscillator clock as refer ence, generating a tick interrupts every 192 clock cycles - four channels of xpwm are running (w aves period: 2, 2.5, 3 and 4 cpu cl ock cycles): no output toggling - five general purpose timers are running in timer mode with prescaler equal to 8 (t2, t3, t4, t5, t6) - adc is in auto scan continuous conv ersion mode on all 16 channels of port5 - all interrupts generated by xpwm, rt c, timers and adc are not serviced 11. the idle mode supply current is a function of the operating frequency (f cpu is expressed in mhz). this dependency is illustrated in the figure 44 below. thes e parameters are tested and at maximum cpu clock with all outputs disconnected and all inputs at v il or v ih , rstin pin at v ih1min . 12. this parameter is tested including leakage currents. a ll inputs (including pins configured as inputs) at 0 to 0.1v or at v dd ? 0.1v to v dd , v aref = 0v, all outputs (including pins configured as outputs) disconnected. furthermore, the main voltage regulator is assumed off: in case it is not, additional 1ma shall be assumed.
electrical characteristics st10f276 182/229 figure 44. port2 test mode structure figure 45. supply current versus the operating frequency (run and idle modes) input latch clock p2.0 cc0io output buffer test mode alternate data input fast external interrupt input flash sense amplifier and column decoder for port2 complete structure refer also to figure 44 . i [ma] f cpu [mhz] 10 20 150 100 50 40 30 50 60 70 0 0 i cc1 i cc2 i id
st10f276 electrical characteristics 183/229 23.6 flash characteristics v dd = 5v 10%, v ss = 0v table 91. flash characteristics parameter typical t a = 25c maximum t a = 125c unit notes 0 cycles (1) 0 cycles (1) 100k cycles word program (32-bit) (2) 35 80 290 s? double word program (64-bit) (2) 60 150 570 s? bank 0 program (384k) (double word program) 2.9 7.4 28.0 s ? bank 1 program (128k) (double word program) 1.0 2.5 9.3 s ? bank 2 program (192k) (double word program) 1.5 3.7 14.0 s ? bank 3 program (128k) (double word program) 1.0 2.5 9.3 s ? sector erase (8k) 0.6 0.5 0.9 0.8 1.0 0.9 s not preprogrammed preprogrammed sector erase (32k) 1.1 0.8 2.0 1.8 2.7 2.5 s not preprogrammed preprogrammed sector erase (64k) 1.7 1.3 3.7 3.3 5.1 4.7 s not preprogrammed preprogrammed bank 0 erase (384k) (3) 8.2 5.8 20.2 17.7 28.6 26.1 s not preprogrammed preprogrammed bank 1 erase (128k) (3) 3.0 2.2 7.0 6.2 9.8 9.0 s not preprogrammed preprogrammed bank 2 erase (192k) (3) 4.3 3.1 10.3 9.1 14.5 13.3 s not preprogrammed preprogrammed bank 3 erase (128k) (3) 3.0 2.2 7.0 6.2 9.8 9.0 s not preprogrammed preprogrammed i-module erase (512k) (4) 11.2 7.6 27.2 23.5 38.4 34.7 s not preprogrammed preprogrammed x-module erase (320k) (4) 7.3 4.9 17.3 14.8 24.3 21.8 s not preprogrammed preprogrammed chip erase (832k) (5) 18.5 12.0 44.4 37.9 62.6 56.1 s not preprogrammed preprogrammed recovery from power-down (t pd ) ?4040 s (6) program suspend latency (6) ?1010 s
electrical characteristics st10f276 184/229 . erase suspend latency (6) ?3030 s erase suspend request rate (6) 20 20 20 ms min delay between two requests set protection (6) 40 170 170 s 1. the figures are given after about 100 cycles due to te sting routines (0 cycles at the final customer). 2. word and double word programming times are provi ded as average value deriv ed from a full sector programming time: absolute value of a word or do uble word programming time could be longer than the provided average value. 3. bank erase is obtained through a multip le sector erase operation (setting bi ts related to all sectors of the bank). 4. module erase is obtained through a sequence of two bank erase operations (since each module is composed by two banks). 5. chip erase is obtained through a sequence of two module erase operations on i- and x-module. 6. not 100% tested, guaranteed by design characterization table 92. data retention characteristics number of program / erase cycles (-40c t a 125c) data retention time (average ambient temperature 60c) 832 kbyte (code store) 64 kbyte (eeprom emulation) (1) 1. two 64 kbyte flash sectors may be typically used to emulate up to 4, 8 or 16 kbytes of eeprom. therefore, in case of an emulation of a 16 kbyt e eeprom, 100000 flash program / erase cycles are equivalent to 800000 eeprom program/erase cycles. for an efficient use of the read while write feature and/or eeprom emulation please refer to dedicated application note document ( an2061 - eeprom emulation with st10f2xx ). contact your local field service, local sales person or stmi croelectronics representative to obt ain a copy of such a guideline document. 0 - 100 > 20 years > 20 years 1000 - > 20 years 10000 - 10 years 100000 - 1 year table 91. flash characteristics (continued) parameter typical t a = 25c maximum t a = 125c unit notes 0 cycles (1) 0 cycles (1) 100k cycles
st10f276 electrical characteristics 185/229 23.7 a/d converter characteristics v dd = 5v 10%, v ss = 0v, t a = ?40 to +125c, 4.5v v aref v dd , v ss v agnd v ss + 0.2v table 93. a/d converter characteristics symbol parameter test condition limit values unit min. max. v aref sr analog reference voltage (1) 1. v aref can be tied to ground when a/d converter is not in use: an extra consumption (around 200 a) on main v dd is added due to internal analog circuitry not comple tely turned off. therefore, it is suggested to maintain the v aref at v dd level even when not in use, and event ually switch off the a/d converter circuitry setting bit ad off in adcon register. 4.5 v dd v v agnd sr analog ground voltage v ss v ss + 0.2 v v ain sr analog input voltage (2) 2. v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be 0x000 h or 0x3ff h , respectively. v agnd v aref v i aref cc reference supply current running mode (3) power down mode 3. not 100% tested, guaranteed by design characterization. ? ? 5 1 ma a t s cc sample time (4) 4. during the sample time, the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to r each its final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming and can be taken from table 94 . 1? s t c cc conversion time (5) 5. this parameter includes the sample time t s , the time for determining the digi tal result and the time to load the result register with the conversion result. values for t he conversion clock t cc depend on programming and can be taken from next table 94 . 3? s dnl cc differential nonlinearity (6) no overload ?1 +1 lsb inl cc integral nonlinearity (6) no overload ?1.5 +1.5 lsb ofs cc offset error (6) no overload ?1.5 +1.5 lsb tue cc total unadjusted error (6) port5 port1 - no overload (3) port1 - overload (3) ?2.0 ?5.0 ?7.0 +2.0 +5.0 +7.0 lsb lsb lsb k cc coupling factor between inputs (3) (7) on both port5 and port1 ?10 ?6 ? c p1 cc input pin capacitance (3) (8) ?3pf c p2 cc port5 port1 ? 4 6 pf pf c s cc sampling capacitance (3)(8) ?3.5pf r sw cc analog switch resistance (3) (8) port5 port1 ? ? 600 1600 w w r ad cc ?1300w
electrical characteristics st10f276 186/229 23.7.1 conversion timing control when a conversion starts, first the capacitances of the converter are loaded via the respec- tive analog input pin to the current analog input voltage. the time to load the capacitances is referred to as sample time. next, the sampled voltage is converted in several successive steps into a digital value, which corresponds to the 10-bit resolution of the adc. during these steps the internal capacitances are repeatedly charged and discharged via the v aref pin. the current that must be drawn from the sources for sampling and changing charges depends on the duration of each step because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. however, the maximum cur- rent that a source can deliver depends on its internal resistance. the time that the two different actions take during conversion (sampling and converting) can be programmed within a certain range in the st10f276 relative to the cpu clock. the abso- lute time consumed by the different conversion steps is therefore independent from the gen- eral speed of the controller. this allows adjusting the st10f276 a/d converter to the properties of the system: fast conversion can be achieved by programming th e respective times to their absolute possible minimum. this is preferable for scanning high frequency signals. however, the internal resistance of analog source and analog supply must be sufficiently low. high internal resistance can be achieved by programming the respective times to a higher value or to the possible maximum. this is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. however, the conversion rate in this case may be considerably lower. the conversion times are programmed via the upper 4 bits of register adcon. bit fields adctc and adstc define the basic conversion ti me and in particular the partition between the sample phase and comparison phases. the table below lists the possible combinations. the timings refer to the unit tcl, where f cpu = 1/2tcl. a complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. 6. dnl, inl, ofs and tue are tested at v aref = 5.0v, v agnd = 0v, v dd = 5.0v. it is guaranteed by design characterization for all other volt ages within the defined voltage range. "lsb" has a value of v aref /1024. for port5 channels, the specified tue ( 2lsb) is also guaranteed with an overload condition (see i ov specification) occurring on a maximum of 2 not sele cted analog input pins of port5 and the absolute sum of input overload currents on all port5 analog input pins does not exceed 10 ma. for port1 channels, the specified tu e is guaranteed when no overload condi tion is applied to port1 pins: when an overload condition oc curs on a maximum of 2 not selected analog input pins of port1 and the input positive overload current on all analog input pins does not exceed 10 ma (either dynamic or static injection), the specified tue is degraded ( 7lsb). to obtain the same accuracy, the negative injection current on port1 pins shall not exceed -1ma in case of both dynamic and static injection. 7. the coupling factor is measured on a channel whil e an overload condition occurs on the adjacent not selected channels with the overload cu rrent within the different spec ified ranges (for both positive and negative injection current). 8. refer to scheme shown in figure 47 table 94. a/d converter programming adctc adstc sample comparison extra total conversion 00 00 tcl * 120 tcl * 240 tcl * 28 tcl * 388 00 01 tcl * 140 tcl * 280 tcl * 16 tcl * 436
st10f276 electrical characteristics 187/229 note: the total conversion time is compatible with the formula valid for st10f269, while the meaning of the bit fields adctc and adstc is no longer compatible: the minimum conversion time is 388 tcl, which at 40 mhz cpu frequency corresponds to 4.85 s (see st10f269). 23.7.2 a/d conversion accuracy the a/d converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (v aref ) and converts it into 10-bit digital data. the absolute accuracy of the a/d conversion is the deviation between the input analog value and the output digital value. it includes the following errors: ? offset error (ofs) ? gain error (ge) ? quantization error ? nonlinearity error (dif ferential and integral) these four error quantities are explained below using figure 46 . offset error offset error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the minimum (zero voltage) 00 to 01 (figure 46, see ofs). gain error gain error is the deviation between the actual and ideal a/d conversion characteristics when the digital output value changes from the 3fe to the maximum 3ff, once offset error is sub- tracted. gain error combined with offset error represents the so-called full-scale error (figure 46, ofs + ge). quantization error quantization error is the intrinsic error of the a/d converter and is expressed as 1/2 lsb. 00 10 tcl * 200 tcl * 280 tcl * 52 tcl * 532 00 11 tcl * 400 tcl * 280 tcl * 44 tcl * 724 11 00 tcl * 240 tcl * 480 tcl * 52 tcl * 772 11 01 tcl * 280 tcl * 560 tcl * 28 tcl * 868 11 10 tcl * 400 tcl * 560 tcl * 100 tcl * 1060 11 11 tcl * 800 tcl * 560 tcl * 52 tcl * 1444 10 00 tcl * 480 tcl * 960 tcl * 100 tcl * 1540 10 01 tcl * 560 tcl * 1120 tcl * 52 tcl * 1732 10 10 tcl * 800 tcl * 1120 tcl * 196 tcl * 2116 10 11 tcl * 1600 tcl * 1120 tcl * 164 tcl * 2884 table 94. a/d converter programming (continued) adctc adstc sample comparison extra total conversion
electrical characteristics st10f276 188/229 nonlinearity error nonlinearity error is the deviation between actual and the best-fitting a/d conversion charac- teristics (see figure 46): ? differential nonlinearity error is the actual step dimension versus the ideal one (1 lsb ideal ). ? integral nonlinearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. note that for integral nonlinearity error, the effect of offset, gain and quantization errors is not included. note: bisector characteristic is obtained drawing a line from 1/2 lsb before the first step of the real characteristic, and 1/2 lsb after the last step again of the real characteristic. 23.7.3 total unadjusted error the total unadjusted error (tue) specifies the maximum deviation from the ideal character- istic: the number provided in the datasheet represents the maximum error with respect to the entire characteristic. it is a combination of the offset, gain and integral linearity errors. the different errors may compensate each other depending on the relative sign of the offset and gain errors. refer to figure 46, see tue. figure 46. a/d conversion characteristic (2) (1) (3) (4) (5) offset error ofs offset error ofs gain error ge 1 lsb (ideal) vain (lsbideal) [lsbideal = varef / 1024] digital out (hex) 3ff 3fe 3fd 3fc 3fb 3fa 005 004 003 002 001 000 007 006 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential nonlinearity error (dnl) (4) integral nonlinearity error (inl) (5) center of a step of the actual transfer curve (6) quantization error (1/2 lsb) (7) total unadjusted error (tue) 1357 1024 1022 1020 1018 246 (6) (7) bisector characteristic ideal characteristic
st10f276 electrical characteristics 189/229 23.7.4 analog reference pins the accuracy of the a/d converter depends on the accuracy of its analog reference: a noise in the reference results in proportionate error in a conversion. a low pass filter on the a/d converter reference source (supplied through pins v aref and v agnd ), is recommended in order to clean the signal, minimizing the nois e. a simple capacitive bypassing may be suffi- cient in most cases; in presence of high rf noise energy, inductors or ferrite beads may be necessary. in this architecture, v aref and v agnd pins also represent the power supply of the analog cir- cuitry of the a/d converter: there is an effective dc current requirement from the reference voltage by the internal resistor string in the r-c dac array and by the rest of the analog cir- cuitry. an external resistance on v aref could introduce error under certain conditions: for this rea- sons, series resistance is not advisable and more generally, any series devices in the filter network should be designed to minimize the dc resistance. 23.7.5 analog input pins to improve the accuracy of the a/d converter, analog input pins must have low ac imped- ance. placing a capacitor with good high freque ncy characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; moreover, its source charges during the sampling phase, when the analog signal source is a high-impedance source. a real filter is typically obtained by using a seri es resistance with a capacitor on the input pin (simple rc filter). the rc filt ering may be limited according to the value of source imped- ance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input sig- nal (bandwidth). figure 47. a/d converter input pins scheme r f c f r s r l r sw c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, cp1 and cp2) c s sampling capacitance c p1 r ad channel selection v a
electrical characteristics st10f276 190/229 input leakage and external circuit the series resistor utilized to limit the current to a pin (see r l in figure 47), in combination with a large source impedance, can lead to a degradation of a/d converter accuracy when input leakage is present. data about maximum input leakage current at each pin is provided in the datasheet (electri- cal characteristics section). input leakage is greatest at high operating temperatures and in general decreases by one half for each 10 c decrease in temperature. considering that, for a 10-bit a/d converter one count is about 5mv (assuming v aref = 5v), an input leakage of 100na acting though an r l = 50k ? of external resistance leads to an error of exactly one count (5mv); if the resistance were 100k ?, the error would become two counts. eventual additional leakage due to external clamping diodes must also be taken into account in computing the total leakage affecting the a/d converter measurements. another contribution to the total leakage is represented by the charge sharing effects with the sam- pling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of a single channel (maximum when fixed channel continuous conver- sion mode is selected), it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 250 khz, with c s equal to 4pf, a resistance of 1m ? is obtained (r eq = 1 / f c c s , where f c represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the following relation: the formula above places constraints on external network design, in particular on resistive path. a second aspect involving the capacitance network must be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit shown in figure 47 ), when the sampling phase is started (a/d switch close), a charge sharing phenomena is installed. figure 48. charge sharing timi ng diagram during sampling phase in particular two different transient periods can be distinguished (see figure 48 ): v a r s r f r l r sw r ad +++ + r eq ------------------------------------------------------------------------------ ? 1 2 -- - lsb < v a v a1 v a2 t t s v cs voltage transient on c s ? v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 )
st10f276 electrical characteristics 191/229 1. a first and quick charge transfer from the internal capacitances c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time cons tant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series and the time constant is: this relation can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to also be robust in the very worst case: the sampling time t s is always much longer than the internal time constant: the charge of c p1 and c p2 is also redistributed on c s , determining a new value of the voltage v a1 on the capacitance according to the following equation: 2. a second charge transfer also involves c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: in this case, the time constant depends on the external circuit: in particular, imposing that the transient is completed well before the end of sampling time t s , a constraint on r l sizing is obtained: of course, r l must also be sized according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being that c f is definitely bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . the following equation must be respected (charge balance assuming now c s already charged at v a1 ): the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, cannot provide the extra charge to compensate for the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing (see figure 49). calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to nyquist theorem the conversion rate f c must be at least 2f 0 , meaning that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion, it is evident that the 1 r sw r ad + () = c p c s ? c p c s + ----------------------- ? 1 r sw r ad + () < c s ? << t s v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? = 2 r l < c s c p1 c p2 ++ () ? 10 2 ? 10 r ? l = c s c p1 c p2 ++ () t s ? v a 2 c s c p1 c p2 c f +++ () ? v a c f ? v a 1 + c p1 c p2 +c s + () ? =
electrical characteristics st10f276 192/229 time constant of the filter r f c f is definitely much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. figure 49. anti-aliasing filter and conversion rate the considerations above lead to impose new c onstraints to the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive the following relation between the ideal and real sampled volt- age on c s : from this formula, in the worst case (when v a is maximum, that is for instance 5v), assum- ing to accept a maximum error of half a count (~2.44mv), it is immediately evident that a constraint is on c f value: the next section provides an example of how to design the external network, based on some reasonable values for the internal parameters and on a hypothesis on the characteris- tics of the analog signal to be sampled. f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f0 fc (nyquist) f f = f 0 (anti-aliasing filtering condition) tc 2 rfcf (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------------ - = c f 2048 c s ? >
st10f276 electrical characteristics 193/229 23.7.6 example of external network sizing the following hypothesis is formulated in order to proceed with designing the external net- work on a/d converter input pins: ? analog signal source bandwidth (f 0 ): 10 khz ? conversion rate (f c ): 25 khz ? sampling time (t s ): 1 s ? pin input capacitance (c p1 ): 5pf ? pin input routing capacitance (c p2 ): 1pf ? sampling capacitance (c s ): 4pf ? maximum input current injection (i inj ): 3ma ? maximum analog source voltage (v am) : 12v ? analog source impedance (r s ): 100 ? ? channel switch resistance (r sw ): 500 ? ? sampling switch resistance (r ad ): 200 ? 1. supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 2. using the relation between c f and c s and taking some margin (4000 instead of 2048), it is possible to define c f : 3. as a consequence of step 1 and 2, rc can be chosen: 4. considering the current injection limitation and supposing that the source can go up to 12v, the total series resistance can be defined as: from which is now simple to define the value of r l : now, the three elements of the external circuit r f , c f and r l are defined. some conditions discussed in the previous paragraphs have be en used to size the component; the others must now be verified. the relation which allows to minimize the accuracy error introduced by the switched capacitance equivalent resistance is in this case: so the error due to the voltage partitioning between the real resistive path and c s is less r c c f 1 2 f 0 ----------- - 15.9 s = = c f 4000 c s ? 16nf = = r f 1 2 f 0 c f ------------------- - 995 ? 1k ? ? = = r s r f r l v am i inj ------------- 4k ? = = ++ r l v am i inj ------------- r f r s 2.9k ? = ? ? = r eq 1 f c c s -------------- - 10m ? = =
electrical characteristics st10f276 194/229 then half a count (considering the worst case when v a = 5v): the other conditions to verify are if the time constants of the transients are really and significantly shorter than the sampling period duration t s : for a complete set of parameters characterizing the st10f276 a/d converter equivalent circuit, refer to a/d converter characteristics table at page 185. 23.8 ac characteristics 23.8.1 test waveforms figure 50. input/output waveforms figure 51. float waveforms v a r s r f r l r sw r ad +++ + r eq ------------------------------------------------------------------------- 2.35mv = ? 1 2 -- - lsb < 1 r sw r ad + () = c s 2.8ns = ? << t s = 1 s 10 2 ? 10r ? l = c s c p1 c p2 ++ () 290ns = ? < t s = 1 s 2.4v 0.4v test points 2.0v 2.0v 0.8v 0.8v ac inputs during testing are driven at 2.4v for a logic ?1? and 0.4v for a logic ?0?. timing measurements are made at v ih min. for a logic ?1? and v il max for a logic ?0?. timing reference points v load + 0.1v v load - 0.1v v oh - 0.1v v ol + 0.1v v load v ol v oh for timing purposes a port pin is no longer floating when v load changes of 100mv occur. it begins to float when a 10 0mv change from the loaded v oh /v ol level occurs (i oh /i ol = 20ma).
st10f276 electrical characteristics 195/229 23.8.2 definition of internal timing the internal operation of the st10f276 is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. the specification of the external timing (ac ch aracteristics) therefore depends on the time between two consecutive edges of the cpu clock, called ?tcl?. the cpu clock signal can be generated by different mechanisms. the duration of tcl and its variation (and also the derived external timing) depends on the mechanism used to generate f cpu . this influence must be regarded when calculating the timings for the st10f276. the example for pll operation shown in figure 52 refers to a pll factor of 4. the mechanism used to generate the cpu clock is selected during reset by the logic levels on pins p0.15-13 (p0h.7-5). figure 52. generation mechanisms for the cpu clock tcl tcl tcl tcl f cpu f xtal f cpu f xtal phase locked loop operation direct clock drive tcl tcl f cpu f xtal prescaler operation
electrical characteristics st10f276 196/229 23.8.3 clock generation modes the following table associates the combinations of these 3 bits with the respective clock generation mode. 23.8.4 prescaler operation when pins p0.15-13 (p0h.7-5) equal ?001? during reset, the cpu clock is derived from the internal oscillator (input cloc k signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f xtal and the high and low time of f cpu (that is, the duration of an individual tcl) is defined by the period of the input clock f xtal . the timings listed in the ac characteristics that refer to tcl can therefore be calculated using the period of f xtal for any tcl. note that if the bit owddis in syscon register is cleared, th e pll runs on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. 23.8.5 direct drive when pins p0.15-13 (p0h.7-5) equal ?011? during reset, the on-chip phase locked loop is disabled, the on-chip oscillator am plifier is bypassed and the cpu clock is directly driven by the input clock signal on xtal1 pin. the frequency of the cpu clock (f cpu ) directly follows the frequency of f xtal so the high and low time of f cpu (that is, the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . table 95. on-chip clock generator selections p0.15-13 (p0h.7-5) cpu frequency f cpu = f xtal x f external clock input range (1)(2) 1. the external clock input range re fers to a cpu clock range of 1...6 4 mhz. moreover, the pll usage is limited to 4-12 mhz input frequency range. all config urations need a crystal (or ceramic resonator) to generate the cpu clock through the inter nal oscillator amplifier (apart fr om direct drive); on the contrary, the clock can be forced through an exte rnal clock s ource only in direct drive mode (on-chip oscillator amplifier disabled, so no crysta l or resonator can be used). 2. the limits on input frequency are 4-12 mhz since the usage of the internal oscillator amplifier is required. also, when the pll is not used and the cpu clock corresponds to f xtal /2, an external crystal or resonator must be used: it is not possible to force any clock though an external clock source. notes 111f xtal x 4 4 to 8 mhz default configuration 110f xtal x 3 5.3 to 10.6 mhz 101f xtal x 8 4 to 8 mhz 100f xtal x 5 6.4 to 12 mhz 011f xtal x 1 1 to 64 mhz direct drive (oscillator bypassed) (3) 3. the maximum depends on the duty cycle of the ex ternal clock signal: when 64 mhz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns ); when 32 mhz is selected, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8ns). 010f xtal x 10 4 to 6.4 mhz 001f xtal / 2 4 to 12 mhz cpu clock via prescaler (3) 000f xtal x 16 4 mhz
st10f276 electrical characteristics 197/229 therefore, the timings given in this chapter refer to the minimum tcl. this minimum value can be calculated by the following formula: for two consecutive tcls, the deviation caused by the duty cycle of f xtal is compensated, so the duration of 2tcl is always 1/f xtal . the minimum value tcl min is used only once for timings that require an odd number of tcls (1, 3, ...). timings that require an even number of tcls (2, 4, ...) may use the formula: the address float timings in multiplexed bus mode (t 11 and t 45 ) use the maximum duration of tcl (tcl max = 1/f xtal x dc max ) instead of tcl min . similarly to what happens for pr escaler operation, if the bit owddis in syscon register is cleared, the pll runs on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. 23.8.6 oscillator watchdog (owd) an on-chip watchdog oscillator is implemented in the st10f276. this feature is used for safety operation with an external crystal osc illator (available only when using direct drive mode with or without prescaler, so the pll is not used to generate the cpu clock multiplying the frequency of the external cr ystal oscillator). this watchdog oscillator operates as following. the reset default configuration enables the watchdog oscillator. it can be disabled by setting the owddis (bit 4) of syscon register. when the owd is enabled, the pll runs at its free-running frequency and it increments the watchdog counter. on each transition of external clock, the watchdog counter is cleared. if an external clock failure occurs, then the watchdog counter overflows (after 16 pll clock cycles). the cpu clock signal is switched to the pll free-running clock signal and the oscillator watchdog interrupt request is flagged. the cpu clock will not sw itch back to the external clock even if a valid external clock exits on xtal1 pin. only a hardware reset (or bidirectional software / watchdog reset) can switch the cpu clock source back to direct clock input. when the owd is disabled, the cpu clock is always the external oscillator clock (in direct drive or prescaler operation) and the pll is switched off to decrease consumption supply current. 23.8.7 phase locked loop (pll) for all other combinations of pins p0.15-13 (p0h.7-5) during reset the on-chip phase locked loop is enabled and it provides the cpu clock (see ta b l e 9 5 ). the pll multiplies the input frequency by the factor f which is selected via the combination of pins p0.15-13 (f cpu = f xtal x f). with every f?th transition of f xtal the pll circuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, so the cpu clock frequency does not change abruptly. tcl min 1f ? xtal l x l dc min = dc = duty cycle 2tcl 1 f xtal ? =
electrical characteristics st10f276 198/229 due to this adaptation to the input clock, the frequency of f cpu is constantly adjusted so it is locked to f xtal . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. the timings listed in the ac characteristics that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. the real minimum value for tcl depends on the jitter of the pll. the pll tunes f cpu to keep it locked on f xtal . the relative deviation of tcl is the maximum when it is referred to one tcl period. this is especially important for bus cycles using wait states and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (such as, for example, pulse train generation or measurement, lower baud rates) the deviation caused by the pll jitter is negligible. refer to next section 23.8.9: pll jitter for more details. 23.8.8 voltage controlled oscillator the st10f276 implements a pll which combines different levels of frequency dividers with a voltage controlled oscillator (vco) working as frequency multiplier. the following table presents a detailed summary of the internal settings and vco frequency. the pll input frequency range is limited to 1 to 3.5 mhz, while the vco oscillation range is 64 to 128 mhz. the cpu clock frequency range when pll is used is 16 to 64 mhz. example 1 ?f xtal = 4 mhz ? p0(15:13) = ?110? (multiplication by 3) ? pll input frequency = 1 mhz ? vco frequency = 48 mhz ? pll output frequency = 12 mhz (vco frequency divided by 4) ?f cpu = 12 mhz (no effect of output prescaler) table 96. internal pll divider mechanism p0.15-13 (p0h.7-5) xtal frequency input prescaler pll output prescaler cpu frequency f cpu = f xtal x f multiply by divide by 1114 to 8mhz f xtal / 4 64 4 ? f xtal x 4 110 5.3 to 10.6 mhz f xtal / 4 48 4 ? f xtal x 3 1014 to 8mhz f xtal / 4 64 2 ? f xtal x 8 1006.4 to 12mhz f xtal / 4 40 2 ? f xtal x 5 0111 to 64mhz ? pll bypassed ? f xtal x 1 0104 to 6.4mhzf xtal / 2 40 2 ? f xtal x 10 0 0 1 4 to 12 mhz ? pll bypassed f pll / 2 f xtal / 2 0004mhz f xtal / 2 64 2 ? f xtal x 16
st10f276 electrical characteristics 199/229 example 2 ?f xtal = 8 mhz ? p0(15:13) = ?100? (multiplication by 5) ? pll input frequency = 2 mhz ? vco frequency = 80 mhz ? pll output frequency = 40 mhz (vco frequency divided by 2) ?f cpu = 40 mhz (no effect of output prescaler) 23.8.9 pll jitter two kinds of pll jitter are defined: self referred single period jitter also called "period jitter", it can be defined as the difference of the t max and t min , where t max is the maximum time period of the pll output clock and t min is the minimum time period of the pll output clock. self referred long term jitter also called "n period jitter", it can be defined as the difference of t max and t min , where t max is the maximum time difference between n + 1 clock rising edges and t min is the minimum time difference between n + 1 clock rising edges. here n should be kept sufficiently large to have the long term jitter. for n = 1, this becomes the single period jitter. jitter at the pll output is caused by: jitter in the input clock noise in the pll loop 23.8.10 jitter in the input clock pll acts like a low pass filter for any jitter in the input clock. input clock jitter with the frequencies within the pll loop bandwidth is passed to the pll output and higher frequency jitter (frequency > pll bandwidth) is attenuated at 20db/decade. 23.8.11 noise in the pll loop this condition again is attr ibuted to the following sources: device noise of the circuit in the pll noise in supply and substrate device noise of the circuit in the pll long term jitter is inversely proportional to the bandwidth of the pll: the wider the loop bandwidth, the lower the jitter due to noise in the loop. moreover, long term jitter is practically independent of the multiplication factor. the most noise sensitive circuit in the pll circuit is definitely the vco (voltage controlled oscillator). there are two ma in sources of noise : thermal (random noise, frequency independent thus practically white noise) and flicker (low frequency noise, 1/f). for the frequency characteristics of the vco circuitry, the effect of the thermal noise results in a 1/f 2 region in the output noise spectrum, while the flicker noise in a 1/f 3 . assuming a noiseless pll input and supposing that the vco is dominated by its 1/f 2 noise, the r.m.s. value of the accumulated jitter is proportional to the square root of n , where n is the number of clock
electrical characteristics st10f276 200/229 periods within the considered time interval. on the contrary, assuming again a noisele ss pll input and supposing that the vco is dominated by its 1/f 3 noise, the r.m.s. value of the accumulated jitter is proportional to n , where n is the number of clock periods within the considered time interval. the jitter in the pll loop can be modelized as dominated by the i1/f 2 noise for n smaller than a certain value depending on the pll output frequency and on the bandwidth characteristics of loop. above this first value, the jitter becomes dominated by the i1/f 3 noise component. lastly, for n greater than a second value of n, a saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods n). the pll loop acts as a high pass filter for any noise in the loop, with cutoff frequency equal to the bandwidth of the pll. the saturation value corresponds to what has been called self referred long term jitter of the pll. in figure 53 the maximum jitter trend versus the number of clock periods n (for some typical cpu frequencies) is shown: the curves represent the very worst case, computed taking into account all corners of temperature, power supply and process variations; the real jitter is always measured well below the given worst case values. noise in supply and substrate digital supply noise adds determining elemen ts to pll output jitter, independent of the multiplication factor. its effect is strongly reduced thanks to particular care used in the physical implementation and integration of the pll module inside the device. in any case, the contribution of digital noise to global jitter is widely taken into account in the curves provided in figure 53 . figure 53. st10f276 pll jitter jitter [ns] n (cpu clock periods) 200 400 5 1 800 600 1000 1200 1400 0 0 64 mhz 2 3 4 24 mhz 40 mhz 32 mhz 16 mhz t jit
st10f276 electrical characteristics 201/229 23.8.12 pll lock/unlock during normal operation, if the pll is unlocked for any reason, an interrupt request to the cpu is generated and the refere nce clock (oscillator) is automa tically disconnected from the pll input: in this way, the pll goes into free-running mode, providing the system with a backup clock signal (free running frequency f free ). this feature allows to recover from a crystal failure occurrence without risking to go into an undefined configuration: the system is provided with a clock allowing the execution of the pll unlock interrupt routine in a safe mode. the path between the reference clock and pll input can be restored only by a hardware reset, or by a bidirectional software or watchdog reset event that forces the rstin pin low. note: the external rc circuit on rstin pin must be the right size in order to extend the duration of the low pulse to grant the pll to be locked before the level at rstin pin is recognized high: bidirectional reset internally drives rstin pin low for just 1024 tcl (definitely not sufficient to get the pll locked starting from free-running mode). conditions: v dd = 5v 10%, t a = ?40 / +125 o c 23.8.13 main oscillator specifications conditions: v dd = 5v 10%, t a = ?40 / +125c table 97. pll lock/unlock timing symbol parameter conditions value unit min. max. t psup pll start-up time (1) 1. not 100% tested, guaranteed by design characterization. stable v dd and reference clock ? 300 s t lock pll lock-in time stable v dd and reference clock, starting from free-running mode ? 250 t jit single period jitter (1) (cycle to cycle = 2 tcl) 6 sigma time period variation (peak to peak) ?500 +500 ps f free pll free running frequency multiplication factors: 3, 4 multiplication factors: 5, 8, 10, 16 250 500 2000 4000 khz table 98. main oscillator specifications symbol parameter conditions value unit min. typ. max. g m oscillator transconductance 8 17 35 ma/v v osc oscillation amplitude (1) 1. not 100% tested, guaranteed by design characterization peak to peak ? v dd ? 0.4 ? v v av oscillation voltage level (1) sine wave middle ? v dd / 2 ?0.25 ? t stup oscillator start-up time (1) stable v dd - crystal ? 3 4 ms stable v dd , resonator ? 2 3
electrical characteristics st10f276 202/229 figure 54. crystal oscillator and resonator connection diagram the given values of c a do not include the stray capacitance of the package and of the printed circuit board: the negative resistance va lues are calculated assuming additional 5pf to the values in the table. the crystal shunt capacitance (c 0 ), the package and the stray capacitance between xtal1 and xtal2 pins is globally assumed equal to 4pf. the external resistance between xtal1 and xtal2 is not necessary, since already present on the silicon. 23.8.14 32 khz oscillator specifications conditions: v dd = 5v 10%, t a = ?40 / +125c table 99. negative resistance (absolute min. value @125 o c / v dd = 4.5v) c a (pf) 12 15 18 22 27 33 39 47 4 mhz 460 ? 550 ? 675 ? 800 ? 840 ? 1000 ? 1180 ? 1200 ? 8 mhz 380 ? 460 ? 540 ? 640 ? 580 ? --- 12 mhz 370 ? 420 ? 360 ? ----- c a c a crystal xtal1 xtal2 resonator xtal1 xtal2 st10f276 st10f276 table 100. 32 khz oscillator specifications symbol parameter conditions value unit min. typ. max. g m32 oscillator (1) 1. at power-on a high current biasing is applied for faster oscillation start-up. once the oscillation is started, the current biasing is reduced to lower the power consumption of the system. start-up 20 31 50 a/v normal run 8 17 30 v osc32 oscillation amplitude (2)) 2. not 100% tested, guaranteed by design characterization. peak to peak 0.5 1.0 2.4 v v av32 oscillation voltage level (2) sine wave middle 0.7 0.9 1.2 t stup32 oscillator start-up time (2) stable v dd ?15s
st10f276 electrical characteristics 203/229 figure 55. 32 khz crystal oscillator connection diagram the given values of c a do not include the stray capacitance of the package and of the printed circuit board: the negative resistance va lues are calculated assuming additional 5pf to the values in the table. the crystal shunt capacitance (c 0 ), the package and the stray capacitance between xtal3 and xtal4 pins is globally assumed equal to 4pf. the external resistance between xtal3 and xtal4 is not necessary, since already present on the silicon. warning: direct driving on xtal3 pin is not supported. always use a 32 khz crystal oscillator. 23.8.15 external clock drive xtal1 when direct drive configuration is selected during reset, it is possible to drive the cpu clock directly from the xtal1 pin, without particular restrictions on the maximum frequency, since the on-chip oscillator amp lifier is bypassed. the speed limit is imposed by internal logic that targets a maximum cpu frequency of 64 mhz. in all other clock configurations (direct drive with prescaler or pll usage) the on-chip oscillator amplifier is not bypassed, so it det ermines the input clock speed limit. then an external clock source can be used but limited in the range of frequencies defined for the usage of crystal and resonator (refer also to table 95 on page 196 ). external clock drive timing conditions: v dd = 5v 10%, v ss = 0v, t a = ?40 to +125c table 101. minimum values of negative resistance (module) c a = 6pf c a = 12pf c a = 15pf c a = 18pf c a = 22pf c a = 27pf c a = 33pf 32khz----150 k ? 120 k ? 90 kw c a c a crystal xtal3 xtal4 st10f276
electrical characteristics st10f276 204/229 figure 56. external clock drive xtal1 note: when direct drive is selected, an external clock source can be used to drive xtal1. the maximum frequency of the external clock source depends on the duty cycle: when 64 mhz is used, 50% duty cycle is granted (low phase = high phase = 7.8ns); when for instance 32 mhz is used, a 25% duty cycle can be acc epted (minimum phase, high or low, again equal to 7.8ns). 23.8.16 memory cycle variables the tables below use three variables which are derived from the busconx registers and represent the special characteristics of the programmed memory cycle. the following table describes how these variables are computed. table 102. external clock drive timing symbol parameter direct drive f cpu = f xtal direct drive with prescaler f cpu = f xtal / 2 pll usage f cpu = f xtal x f unit min. max. min. max. min. max. t osc sr xtal1 period (1) (2) 1. the minimum value for the xtal1 signal period is co nsidered as the theoretical minimum. the real minimum value depends on the duty cycle of the input clock signal. 2. 4-12 mhz is the input frequency r ange when using an external clock s ource. 64 mhz can be applied with an external clock source only when dire ct drive mode is selected: in this case, the oscillator amplifier is bypassed so it does not limit the input frequency. 15.625 ? 83.3 250 83.3 250 ns t 1 sr high time (3) 3. the input clock signal must reach the defined levels v il2 and v ih2 . 6 ?3?6? t 2 sr low time (3) t 3 sr rise time (3) ?2?2?2 t 4 sr fall time (3) t 1 t 3 t 4 v il2 t 2 t osc v ih2 table 103. memory cycle variables symbol description values t a ale extension tcl x [alectl] t c memory cycle time wait states 2tcl x (15 - [mctc]) t f memory tri-state time 2tcl x (1 - [mttc])
st10f276 electrical characteristics 205/229 23.8.17 external memory bus timing in the next sections the external memory bus timings are described. the given values are computed for a maximum cpu clock of 40 mhz. it is evident that when higher cpu clock frequen cy is used (up to 64 mhz), some numbers in the timing formulas become zero or negative, which in most cases is not acceptable or meaningful. in these cases, the speed of the bus settings t a , t c and t f must be correctly adjusted. note: all external memory bus timings and ssc timings presented in the following tables are given by design characterization and not fully tested in production.
electrical characteristics st10f276 206/229 23.8.18 multiplexed bus v dd = 5v 10%, v ss = 0v, t a = ?40 to +125c, c l = 50pf, ale cycle time = 6 tcl + 2t a + t c + t f (75ns at 40 mhz cpu clock without wait states). table 104. multiplexed bus symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 64 mhz unit min. max. min. max. t 5 cc ale high time 4 + t a ? tcl ? 8.5 + t a ? ns t 6 cc address setup to ale 1.5 + t a tcl ? 11 + t a t 7 cc address hold after ale 4 + t a tcl ? 8.5 + t a t 8 cc ale falling edge to rd , wr (with rw-delay) 4 + t a tcl ? 8.5 + t a t 9 cc ale falling edge to rd , wr (no rw-delay) ? 8.5 + t a ? 8.5 + t a t 10 cc address float after rd , wr (with rw-delay) (1) ? 6 ? 6 t 11 cc address float after rd , wr (no rw-delay)1 18.5 tcl + 6 t 12 cc rd , wr low time (with rw-delay) 15.5 + t c ? 2tcl ? 9.5 + t c ? t 13 cc rd , wr low time (no rw-delay) 28 + t c 3tcl ? 9.5 + t c t 14 sr rd to valid data in (with rw-delay) ? 6 + t c ? 2tcl ? 19 + t c t 15 sr rd to valid data in (no rw-delay) 18.5 + t c 3tcl ? 19 + t c t 16 sr ale low to valid data in 17.5 + + t a + t c 3tcl ? 20 + + t a + t c t 17 sr address/unlatched cs to valid data in 20 + 2t a + + t c 4tcl ? 30 + + 2t a + t c t 18 sr data hold after rd rising edge 0? 0 ? t 19 sr data float after rd 1 ? 16.5 + t f ? 2tcl ? 8.5 + t f t 22 cc data valid to wr 10 + t c ? 2tcl ? 15 + t c ? t 23 cc data hold after wr 4 + t f 2tcl ? 8.5 + t f t 25 cc ale rising edge after rd , wr 15 + t f 2tcl ? 10 + t f t 27 cc address/unlatched cs hold after rd , wr 10 + t f 2tcl ? 15 + t f
st10f276 electrical characteristics 207/229 t 38 cc ale falling edge to latched cs ? 4 ? t a 10 ? t a ? 4 ? t a 10 ? t a ns t 39 sr latched cs low to valid data in ? 16.5 + t c + 2t a ? 3tcl? 21+ t c + 2t a t 40 cc latched cs hold after rd , wr 27 + t f ? 3tcl ? 10.5 + t f ? t 42 cc ale fall. edge to rdcs , wrcs (with rw delay) 7 + t a tcl ? 5.5 + t a t 43 cc ale fall. edge to rdcs , wrcs (no rw delay) ? 5.5 + t a ? 5.5 + t a t 44 cc address float after rdcs , wrcs (with rw delay)1 ? 1.5 ? 1.5 t 45 cc address float after rdcs , wrcs (no rw delay) 14 tcl + 1.5 t 46 sr rdcs to valid data in (with rw delay) 4 + t c 2tcl ? 21 + t c t 47 sr rdcs to valid data in (no rw delay) 16.5 + t c 3tcl ? 21 + t c t 48 cc rdcs , wrcs low time (with rw delay) 15.5 + t c ? 2tcl ? 9.5 + t c ? t 49 cc rdcs , wrcs low time (no rw delay) 28 + t c 3tcl ? 9.5 + t c t 50 cc data valid to wrcs 10 + t c 2tcl ? 15 + t c t 51 sr data hold after rdcs 00 t 52 sr data float after rdcs (1) ? 16.5 + t f ? 2tcl ? 8.5 + t f t 54 cc address hold after rdcs , wrcs 6 + t f ? 2tcl ? 19 + t f ? t 56 cc data hold after wrcs 1. partially tested, guaranteed by design characterization. table 104. multiplexed bus (continued) symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 64 mhz unit min. max. min. max.
electrical characteristics st10f276 208/229 figure 57. multiplexed bus with/without r/w delay and normal ale data in data out address address t 38 t 10 read cycle write cycle t 5 t 16 t 39 t 40 t 25 t 27 t 18 t 14 t 22 t 23 t 12 t 8 t 8 t 6m t 19 address t 17 t 6 t 7 t 9 t 11 t 13 t 15 t 16 t 12 t 13 address t 9 t 17 t 6 t 27 clkout ale csx a23-a16 (a15-a8) address/data rd wr wrl bhe wrh bus (p0) address/data bus (p0)
st10f276 electrical characteristics 209/229 figure 58. multiplexed bus with/without r/w delay and extended ale data out address data in address address t 5 t 16 t 6 t 7 t 39 t 40 t 14 t 8 t 18 t 23 t 6 t 27 t 38 t 10 t 19 t 25 t 17 t 9 t 11 t 15 t 12 t 13 t 8 t 10 t 9 t 11 t 12 t 13 t 22 t 27 t 17 t 6 read cycle write cycle clkout ale csx a23-a16 (a15-a8) rd wr wrl bhe wrh address/data bus (p0) address/data bus (p0)
electrical characteristics st10f276 210/229 figure 59. multiplexed bus, with/without r/w delay, normal ale, r/w cs read cycle write cycle clkout ale a23-a16 (a15-a8) bhe data in data out address address t 44 t 5 t 16 t 25 t 27 t 51 t 46 t 50 t 56 t 48 t 42 t 42 t 6 t 52 address t 17 t 6 t 7 t 43 t 45 t 49 t 47 t 16 t 48 t 49 address t 43 rdcsx wrcsx address/data bus (p0) address/data bus (p0)
st10f276 electrical characteristics 211/229 figure 60. multiplexed bus, with/without r/ w delay, extended ale, r/w cs data out address data in address address t 5 t 16 t 6 t 7 t 46 t 42 t 42 t 50 t 18 t 56 t 6 t 54 t 44 t 19 t 25 t 17 t 43 t 45 t 47 t 48 t 49 t 49 t 43 t 48 t 44 t 45 read cycle write cycle clkout ale a23-a16 (a15-a8) bhe rdcsx wrcsx address/data bus (p0) address/data bus (p0)
electrical characteristics st10f276 212/229 23.8.19 demultiplexed bus v dd = 5v 10%, v ss = 0v, t a = ?40 to +125c, c l = 50pf, ale cycle time = 4 tcl + 2t a + t c + t f (50ns at 40 mhz cpu clock without wait states). table 105. demultiplexed bus symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 64 mhz unit min. max. min. max. t 5 cc ale high time 4 + t a ? tcl ? 8.5 + t a ? ns t 6 cc address setup to ale 1.5 + t a ? tcl ? 11 + t a ? ns t 80 cc address/unlatched cs setup to rd , wr (with rw-delay) 12.5 + 2t a ? 2tcl ? 12.5 + 2t a ? ns t 81 cc address/unlatched cs setup to rd , wr (no rw-delay) 0.5 + 2t a ? tcl ? 12 + 2t a ? ns t 12 cc rd , wr low time (with rw-delay) 15.5 + t c ? 2tcl ? 9.5 + t c ? ns t 13 cc rd , wr low time (no rw-delay) 28 + t c ? 3tcl ? 9.5 + t c ? ns t 14 sr rd to valid data in (with rw-delay) ?6 + t c ? 2tcl ? 19 + t c ns t 15 sr rd to valid data in (no rw-delay) ? 18.5 + t c ? 3tcl ? 19 + t c ns t 16 sr ale low to valid data in ? 17.5 + t a + t c ? 3tcl ? 20 + t a + t c ns t 17 sr address/unlatched cs to valid data in ? 20 + 2 t a + t c ? 4tcl ? 30 + 2 t a + t c ns t 18 sr data hold after rd rising edge 0? 0 ? ns t 20 sr data float after rd rising edge (with rw-delay) 3 (1) ? 16.5 + t f ? 2tcl ? 8.5 + t f + 2 t a ns t 21 sr data float after rd rising edge (no rw- delay) 1 ?4 + t f ? tcl ? 8.5 + t f + 2 t a ns t 22 cc data valid to wr 10 + t c ? 2tcl ? 15 + t c ? ns t 24 cc data hold after wr 4 + t f ? tcl ? 8.5 + t f ? ns t 26 cc ale rising edge after rd , wr ?10 + t f ? ?10 + t f ? ns t 28 cc address/unlatched cs hold after rd , wr (2) 0 + t f ?0 + t f ? ns t 28h cc address/unlatched cs hold after wrh ? 5 + t f ? ? 5 + t f ? ns
st10f276 electrical characteristics 213/229 1 partially tested, guaranteed by design characterization. the following figures ( figure 57 to figure 64 ) present the different configurations of external memory cycle. t 38 cc ale falling edge to latched cs ? 4 ? t a 6 ? t a ? 4 ? t a 6 ? t a ns t 39 sr latched cs low to valid data in ? 16.5 + t c + 2 t a ? 3tcl ? 21+ t c + 2 t a ns t 41 cc latched cs hold after rd , wr 2 + t f ? tcl ? 10.5 + t f ? ns t 82 cc address setup to rdcs , wrcs (with rw-delay) 14 + 2t a ? 2tcl ? 11 + 2t a ? ns t 83 cc address setup to rdcs , wrcs (no rw-delay) 2 + 2t a ? tcl ?10.5 + 2t a ? ns t 46 sr rdcs to valid data in (with rw-delay) ?4 + t c ? 2tcl ? 21 + t c ns t 47 sr rdcs to valid data in (no rw-delay) ? 16.5 + t c ? 3tcl ? 21 + t c ns t 48 cc rdcs , wrcs low time (with rw-delay) 15.5 + t c ? 2tcl ? 9.5 + t c ? ns t 49 cc rdcs , wrcs low time (no rw-delay) 28 + t c ? 3tcl ? 9.5 + t c ? ns t 50 cc data valid to wrcs 10 + t c ? 2tcl ? 15 + t c ? ns t 51 sr data hold after rdcs 0? 0 ? ns t 53 sr data float after rdcs (with rw-delay) ? 16.5 + t f ? 2tcl ? 8.5 + t f ns t 68 sr data float after rdcs (no rw-delay) ? 4 + t f ? tcl ? 8.5 + t f ns t 55 cc address hold after rdcs , wrcs ? 8.5 + t f ? ? 8.5 + t f ? ns t 57 cc data hold after wrcs 2 + t f ? tcl ? 10.5 + t f ? ns 1. rw-delay and t a refer to the next following bus cycle. 2. read data is latched with the same clock edge that triggers the address change and the rising rd edge. therefore address changes which occur before the end of rd have no impact on read cycles. table 105. demultiplexed bus (continued) symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 64 mhz unit min. max. min. max.
electrical characteristics st10f276 214/229 figure 61. demultiplexed bus, with/wi thout read/write delay and normal ale write cycle clkout ale a23-a16 a15-a0 (p1) bhe wr wrl wrh data in data out t 38 t 5 t 16 t 39 t 41 t 18 t 14 t 22 t 12 address t 17 t 13 t 15 t 12 t 13 t 21 t 20 t 81 t 80 t 26 t 24 t 17 t 6 t 41u t 6 t 80 t 81 t 28 (or t 28h) csx read cycle data bus (p0) rd 1) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 1) un-latched csx = t 41u = t 41 tcl =10.5 + t f .
st10f276 electrical characteristics 215/229 figure 62. demultiplexed bus with/without r/w delay and extended ale address t 5 t 16 t 39 t 41 t 14 t 24 t 6 t 38 t 20 t 26 t 17 t 15 t 12 t 13 t 12 t 13 t 22 data in t 18 t 21 t 6 t 17 t 28 t 28 data out t 80 t 81 t 80 t 81 read cycle write cycle clkout ale csx rd wr wrl wrh data bus (p0) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 a23-a16 a15-a0 (p1) bhe
electrical characteristics st10f276 216/229 figure 63. demultiplexed bus with ale and r/w cs read cycle write cycle clkout ale data in data out t 5 t 16 t 51 t 46 t 50 t 48 address t 17 t 49 t 47 t 48 t 49 t 68 t 53 t 83 t 82 t 26 t 57 t 55 t 6 t 82 t 83 rdcsx wrcsx data bus (p0) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 a23-a16 a15-a0 (p1) bhe
st10f276 electrical characteristics 217/229 figure 64. demultiplexed bus, no r/w delay, extended ale, r/w cs address t 5 t 16 t 46 t 57 t 6 t 53 t 26 t 17 t 47 t 48 t 49 t 48 t 49 t 50 data in t 51 t 68 t 55 data out t 82 t 83 t 82 t 83 read cycle write cycle clkout ale rdcsx wrcsx data bus (p0) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 a23-a16 a15-a0 (p1) bhe
electrical characteristics st10f276 218/229 23.8.20 clkout and ready v dd = 5v 10%, v ss = 0v , t a = -40 to + 125c, c l = 50pf table 106. clkout and ready symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 64 mhz unit min. max. min. max. t 29 cc clkout cycle time 25 25 2tcl 2tcl ns t 30 cc clkout high time 9 ? tcl ? 3.5 ? t 31 cc clkout low time 10 tcl ? 2.5 t 32 cc clkout rise time ?4 ? 4 t 33 cc clkout fall time t 34 cc clkout rising edge to ale falling edge ? 2 + t a 8 + t a ? 2 + t a 8 + t a t 35 sr synchronous ready setup time to clkout 17 ? 17 ? t 36 sr synchronous ready hold time after clkout 22 t 37 sr asynchronous ready low time 35 2tcl + 10 t 58 sr asynchronous ready setup time (1) 1. these timings are given for characterization purposes only, in order to assure recognition at a specific clock edge. 17 17 t 59 sr asynchronous ready hold time (1) 22 t 60 sr async. ready hold time after rd , wr high (demultiplexed bus) (2) 2. demultiplexed bus is the worst case. for multiplexed bus 2tcls must be added to the maximum values. this adds even more time for deactivating ready. 2t a and t c refer to the next following bus cycle and t f refers to the current bus cycle. 02t a + tc + t f 02t a + tc + t f
st10f276 electrical characteristics 219/229 figure 65. clkout and ready 1. cycle as programmed, including mctc wait states (example shows 0 mctc ws). 2. the leading edge of the respective command depends on rw-delay. 3. ready sampled high at this sampling point generates a ready controlled wait state, ready sampled low at this sampling point terminat es the currently running bus cycle. 4. ready may be deactivated in response to the traili ng (rising) edge of the corresponding command (rd or wr ). 5. if the asynchronous ready signal does not fulfill the indicated setup and hold times with respect to clkout (for example, because clkout is not enabled), it must fulfill t 37 in order to be safely synchronized. this is guaranteed if ready is remo ved in response to the command (see note 4). 6. multiplexed bus modes have a mux wait state added a fter a bus cycle, and an additional mttc wait state may be inserted here. for a multiplexed bus with mttc wait state this delay is 2 clkout cycles; for a demultiplexed bus without mttc wait state this delay is zero. 7. the next external bus cycle may start here. t 30 t 34 t 35 t 36 t 35 t 36 t 58 t 59 t 58 t 59 wait state ready mux / tri-state 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) t 60 4) 6) 2) 7) 3) 3) clkout ale rd , wr synchronous asynchronous ready ready
electrical characteristics st10f276 220/229 23.8.21 external bus arbitration v dd = 5v 10%, v ss = 0v , t a = -40 to +125c, c l = 50pf figure 66. external bus arbitration (releasing the bus) 1. the st10f276 will complete the currently r unning bus cycle before granting bus access. 2. this is the first possibility for breq to become active. 3. the cs outputs will be resistive high (pull-up) after t 64 . table 107. external bus arbitration symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 64 mhz unit min. max. min. max. t 61 sr hold input setup time to clkout 18.5 ? 18.5 ? ns t 62 cc clkout to hlda high or breq low delay ? 12.5 ? 12.5 t 63 cc clkout to hlda low or breq high delay t 64 cc csx release 1 20 20 t 65 cc csx drive ? 4 15 ? 4 15 t 66 cc other signals release 1 ?20 ? 20 t 67 cc other signals drive ? 4 15 ? 4 15 t 61 t 63 t 66 (1) t 64 1) 2) t 62 3) clkout hold hlda breq others csx (p6.x)
st10f276 electrical characteristics 221/229 figure 67. external bus arbitration (regaining the bus) 1. this is the last chance for breq to trigger the indicated regain-sequence. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be deactivated without the st10f276 requesting the bus. 2. the next st10f276 driven bus cycle may start here. t 62 t 67 t 62 t 65 t 61 t 63 t 62 1) 2) hlda hold clkout breq csx (on p6.x) other signals
electrical characteristics st10f276 222/229 23.8.22 high-speed synchronous serial interface (ssc) timing modes master mode v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, c l = 50pf table 108. master mode symbol parameter max. baud rate 6.6mbd (1) @f cpu = 40 mhz ( = 0002h) 1. maximum baud rate is in reality 8mbaud, that can be reached with 64 mhz cpu clock and set to ?3h?, or with 48 mhz cpu clock and set to ?2h?. when 40 mhz cpu clock is used the maximum baud rate cannot be higher than 6.6mbaud ( = ? 2h?) due to the limited gr anularity of . value ?1h? for may be used only with cpu cl ock equal to (or lower than) 32 mhz (after checking that timings are in line with the target slave). variable baud rate ( = 0001h - ffffh) unit min. max. min. max. t 300 cc ssc clock cycle time (2) 2. formula for ssc clock cycle time: t 300 = 4 tcl x ( + 1) where represents the content of the ssc baud rate register, taken as unsigned 16-bit integer. minimum limit allowed for t 300 is 125ns (corresponding to 8mbaud) 150 150 8tcl 262144 tcl ns t 301 cc ssc clock high time 63 ? t 300 / 2 ? 12 ? t 302 cc ssc clock low time t 303 cc ssc clock rise time ? 10 ? 10 t 304 cc ssc clock fall time t 305 cc write data valid after shift edge 15 15 t 306 cc write data hold after shift edge 3 ? 2 ? ? 2 ? t 307p sr read data setup time before latch edge, phase error detection on (sscpen = 1) 37.5 2tcl + 12.5 t 308p sr read data hold time after latch edge, phase error detection on (sscpen = 1) 50 4tcl t 307 sr read data setup time before latch edge, phase error detection off (sscpen = 0) 25 2tcl t 308 sr read data hold time after latch edge, phase error detection off (sscpen = 0) 00
st10f276 electrical characteristics 223/229 figure 68. ssc master timing 1. the phase and polarity of shift and latch edge of sclk is programmable. this fi gure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (sscph = 0b), idle clock line is low, leading clock edge is low-to-high transition (sscpo = 0b). 2. the bit timing is repeated for all bi ts to be transmitted or received. 1st out bit last out bit 2nd out bit 2nd in bit 1st in bit sclk mtsr mrst (1) (2) t 308 t 307 t 308 t 307 t 305 t 305 t 306 t 305 t 304 t 303 t 300 t 301 t 302 last in bit
electrical characteristics st10f276 224/229 slave mode v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, c l = 50pf table 109. slave mode symbol parameter max. baud rate 6.6 mbd (1) @f cpu = 40 mhz ( = 0002h) 1. maximum baud rate is in reality 8mbaud, that can be reached with 64 mhz cpu clock and set to ?3h?, or with 48 mhz cpu clock and set to ?2h?. when 40 mhz cpu clock is used the maximum baud rate cannot be higher than 6.6mbaud ( = ? 2h?) due to the limited gr anularity of . value ?1h? for may be used only with cpu clock lower than 32 mhz (after checking that timings are in line with the target master). variable baud rate ( = 0001h - ffffh) unit min. max. min. max. t 310 sr ssc clock cycle time (2) 2. formula for ssc clock cycle time: t 310 = 4 tcl * ( + 1) where represents the content of the ssc baud rate register, taken as unsigned 16-bit integer. minimum limit allowed for t 310 is 125ns (corresponding to 8mbaud). 150 150 8tcl 262144 tcl ns t 311 sr ssc clock high time 63 ? t 310 / 2 ? 12 ? t 312 sr ssc clock low time t 313 sr ssc clock rise time ? 10 ? 10 t 314 sr ssc clock fall time t 315 cc write data valid after shift edge 55 2tcl + 30 t 316 cc write data hold after shift edge 0 ? 0 ? t 317p sr read data setup time before latch edge, phase error detection on (sscpen = 1) 62 4tcl + 12 t 318p sr read data hold time after latch edge, phase error detection on (sscpen = 1) 87 6tcl + 12 t 317 sr read data setup time before latch edge, phase error detection off (sscpen = 0) 66 t 318 sr read data hold time after latch edge, phase error detection off (sscpen = 0) 31 2tcl + 6
st10f276 electrical characteristics 225/229 figure 69. ssc slave timing 1. the phase and polarity of shift and latch edge of sclk is programmable. this fi gure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (sscph = 0b), idle clock line is low, leading clock edge is low-to-high transition (sscpo = 0b). 2. the bit timing is repeated for all bi ts to be transmitted or received. 1st out bit last out bit 2nd out bit 1) 2) 2nd in bit 1st in bit last in bit sclk mrst mtsr t 315 t 315 t 315 t 316 t 318 t 317 t 317 t 318 t 310 t 311 t 312 t 313 t 314 (2) (1)
package information st10f276 226/229 24 package information figure 70. 144-pin plastic quad flat package pqfp144 dim. mm inch min. typ. max. min. typ. max. a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.135 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 e3 22.75 0.896 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) a a2 a1 b c 36 37 72 73 108 109 144 e3 d3 e1 e d1 d e 1 k b pqfp144 l l1 seating plane 0.10mm .004 outline and mechanical data
st10f276 package information 227/229 figure 71. 144-pin low profile quad flat package (10x10) dim. mm inches (1) 1.values in inches are converted from mm and rounded to 3 decimal digits. min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.057 b 0.17 0.22 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 21.80 22.00 22.20 0.858 0.867 0.874 d1 19.80 20.00 20.20 0.780 0.787 0.795 d3 17.50 0.689 e 21.80 22.00 22.20 0.858 0.867 0.874 e1 19.80 20.00 20.20 0.780 0.787 0.795 e3 17.50 0.689 e 0.50 0.020 k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 144 a a2 a1 b c 36 37 72 73 108 109 144 e1 e d1 d 1 h b l l1 seating plane 0.08 mm .003 in. e e3 d3
revision history st10f276 228/229 25 revision history table 110. document revision history date revision changes 02-june-2006 1 initial release.
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